The 2nd Generation Intel® Hyperflex™ FPGA fabric incorporated into all Intel® Agilex™ FPGAs boosts Fmax by as much as 40% and cuts power by as much as 40%. Now you can attend one of two free, one-hour Webinars on November 7 or November 12 that discuss this innovation in FPGA design. The November 7 Webinar is scheduled to be most convenient for North and South America and will be held at 9 AM Pacific Time. The November 12 Webinar is scheduled to most convenient for Europe and will be held at 10 AM Central European Time.
Both Webinars include an overview of three specific design techniques you can use to take advantage of the Hyper-Registers in the Intel Hyperflex architecture:
Marlon Price, an Intel Applications Engineer with more than 18 years of FPGA design and instruction experience under his belt, is presenting both Webinars. Price’s specialties include high-end FPGA design optimization, high-speed serial protocols and interfaces, 5G applications, and algorithm acceleration using FPGAs. You are going to want to hear what he has to say.
Click here to register for the November 7 Webinar.
Click here to register for the November 12 Webinar.
For more information about the 2nd Generation Intel Hyperflex Architecture, see “2nd Generation Intel® Hyperflex™ FPGA fabric in Intel® Agilex™ FPGAs boosts Fmax by as much as 40% and cuts power, also by as much as 40%
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