Good news: Second free Webinar about 2nd Generation Intel® Hyperflex™ Architecture for Intel Agilex™ FPGAs added. November 7 and 12

The 2nd Generation Intel® Hyperflex™ FPGA fabric incorporated into all Intel® Agilex™ FPGAs boosts Fmax by as much as 40% and cuts power by as much as 40%. Now you can attend one of two free, one-hour Webinars on November 7 or November 12 that discuss this innovation in FPGA design. The November 7 Webinar is scheduled to be most convenient for North and South America and will be held at 9 AM Pacific Time. The November 12 Webinar is scheduled to most convenient for Europe and will be held at 10 AM Central European Time.

Both Webinars include an overview of three specific design techniques you can use to take advantage of the Hyper-Registers in the Intel Hyperflex architecture:

  • Hyper-Retiming
  • Hyper-Pipelining
  • Hyper-Optimization

Marlon Price, an Intel Applications Engineer with more than 18 years of FPGA design and instruction experience under his belt, is presenting both Webinars. Price’s specialties include high-end FPGA design optimization, high-speed serial protocols and interfaces, 5G applications, and algorithm acceleration using FPGAs. You are going to want to hear what he has to say.


Click here to register for the November 7 Webinar.

Click here to register for the November 12 Webinar.


For more information about the 2nd Generation Intel Hyperflex Architecture, see “2nd Generation Intel® Hyperflex™ FPGA fabric in Intel® Agilex™ FPGAs boosts Fmax by as much as 40% and cuts power, also by as much as 40%



Legal Notices and Disclaimers:

Intel technologies’ features and benefits depend on system configuration and may require enabled hardware, software or service activation. Performance varies depending on system configuration. No product or component can be absolutely secure. Check with your system manufacturer or retailer or learn more at

Results have been estimated or simulated using internal Intel analysis, architecture simulation and modeling, and provided to you for informational purposes. Any differences in your system hardware, software or configuration may affect your actual performance.

Intel does not control or audit third-party data. You should review this content, consult other sources, and confirm whether referenced data are accurate.

Cost reduction scenarios described are intended as examples of how a given Intel- based product, in the specified circumstances and configurations, may affect future costs and provide cost savings.

Circumstances will vary. Intel does not guarantee any costs or cost reduction.

© Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries.  Other names and brands may be claimed as the property of others.


Published on Categories AgilexTags
Steven Leibson

About Steven Leibson

Be sure to add the Intel Logic and Power Group to your LinkedIn groups. Steve Leibson is a Senior Content Manager at Intel. He started his career as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He’s served as Editor in Chief of EDN Magazine and Microprocessor Report and was the founding editor of Wind River’s Embedded Developers Journal. He has extensive design and marketing experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.