Future-proof your system design with the broad line of Intel® FPGA, Intel eASIC™ devices and Intel Enpirion® Power Solutions

With a little up-front planning, you can design a future-proof system that starts with an FPGA logic implementation, then switches to a footprint-compatible Intel® eASIC™ device, and then jumps to full-custom ASIC as system sales volumes grow – and you can do all of this with the same PCB design. Many design engineers already know about the logic options described above, but there’s another interesting facet to future-proofed system design that involves the board-level power supplies. FPGAs, Intel eASIC devices, and custom ASICs all have different power-rail requirements with respect to voltage levels, voltage regulation, noise and ripple, and current consumption. Using Intel Enpirion® power solutions, the same PCB design can also accommodate the power needs for FPGAs, eASIC devices, and custom ASICs.

If you’re not already familiar with Intel Enpirion PowerSoCs, they’re a family of small, high-efficiency point-of-load (POL) power devices that can help you meet stringent power-rail voltage, noise, and ripple requirements; constrained thermal and power budgets; and demanding PCB area constraints. The figure below illustrates the flexibility that footprint-compatible Intel Enpirion power solutions can provide.

 

Note: You can parallel as many as four EC2650QI devices as needed

 

For all of the logic devices in question – FPGAs, eASIC devices, and ASICs – the core power supply draws the most current. As the figure shows, the 40 A Intel Enpirion EM2140 could power the FPGA’s core power rail. After transitioning from an FPGA to an eASIC device, you could then replace the 40 A EM2140 PowerSoc with the lower power, footprint-compatible 30 A EM2130 device without re-spinning your board. Beyond the EM2140 and EM2130 PowerSoCs, the Intel Enpirion Power portfolio offers a large selection of other footprint-compatible solutions that can meet the logic devices’ supply voltage requirements for core, memory, transceiver, I/O, and auxiliary supplies. Some examples are shown in the figure and you can find a complete list in the solution brief attached below. These footprint-compatible Intel Enpirion PowerSoCs can save system power and reduce system BOM cost while future-proofing your design.

For more information, see the Intel Enpirion Solution Brief titled “Powering Intel eASIC Devices.”

 

Intel, the Intel Logo, Intel eASIC, and Intel Enpirion are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries.

Published on Categories eASIC, Enpirion, PowerSoCTags , ,
Steven Leibson

About Steven Leibson

Be sure to add the Intel Logic and Power Group to your LinkedIn groups. Steve Leibson is a Senior Content Manager at Intel. He started his career as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He’s served as Editor in Chief of EDN Magazine and Microprocessor Report and was the founding editor of Wind River’s Embedded Developers Journal. He has extensive design and marketing experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.