Free Webinar: Unlock the Benefits of Time Sensitive Networking (TSN) with FPGAs in Industrial Applications

Time-Sensitive Networking (TSN) – the evolving set of IEEE standards that support a mix of deterministic, real-time and best-effort traffic over fast Ethernet connections – provides precise time synchronization of network nodes using synchronized, distributed local clocks. It’s increasingly being used for smart factories, Industry 4.0, and Intelligent Internet of Things (IIoT) applications. If you want to build TSN into your equipment designs, Intel® FPGAs are a good choice.

Looking for an easy way to wade into the topic? Intel and Arrow have you covered with a free Webinar titled: “Unlock the Benefits of Time Sensitive Networking (TSN) with FPGAs in Industrial Applications,” presented by Dr. Joshua Levine from Intel and Dr. Patrick Loschmidt from TTTech.

The Webinar covers:

 

  • What TSN is and how it works
  • The Open Platform Communications (OPC) Unified Architecture (UA)
  • How TSN can be used for Industrial Automation and other applications
  • The Intel TSN offering
  • Detailed look at TSN solutions based on Intel FPGAs

 

The Webinar kicks off on October 19, but even if you can’t make that date and time, register anyway and you’ll get access to a recording of the presentation so that you can watch at your convenience.

Register here.

 

For more information about TSN and Intel FPGAs, see “IEEE 802.1 TSN IP and software from TTTech Industrial now available packaged with selected Cyclone® V SoC FPGAs.”

 

 

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Published on Categories Cyclone, NetworkingTags ,
Steven Leibson

About Steven Leibson

Be sure to add the Intel Logic and Power Group to your LinkedIn groups. Steve Leibson is a Senior Content Manager at Intel. He started his career as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He’s served as Editor in Chief of EDN Magazine and Microprocessor Report and was the founding editor of Wind River’s Embedded Developers Journal. He has extensive design and marketing experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.