Free Webinar: Solving the Power Challenges of High-Performance FPGAs, ASICs, and SoCs

High-performance FPGAs, ASICs, SoCs promise to deliver more capability than ever before, but they need solid, reliable power to deliver on that promise. The power requirements of these advanced processors present new design challenges with rigorous performance requirements and tighter power and thermal budgets. You must meet all these design challenges, on time and on budget.

Learn how to solve these challenges to leverage the increasing capability of next generation high-performance systems. In a free, one-hour Webinar, the Intel® Enpirion® Power group will discuss design tips and solutions to power systems with current requirements of 200 A or more and will cover how to select power solutions that:

 

  • Deliver Low Risk & Fast TTM: Designed, tested, and fully validated with Intel FPGAs – mitigating delays in design schedule and costly redesigns
  • Meet tight performance specs: Including accuracy and ripple, fast transient, and high efficiency
  • Provide Scalability: Footprint compatible solutions which enable design flexibility and can ultimately lead to cost reductions through BOM optimization

 

Webinar Date: Thursday, June 25, 2020

Webinar Time: 9:00 AM – 10:00 AM PDT

 

Register here.

 

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Notices & Disclaimers

Intel technologies may require enabled hardware, software or service activation.

No product or component can be absolutely secure.

Your costs and results may vary.

© Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others.

 

 

Published on Categories EnpirionTags
Steven Leibson

About Steven Leibson

Be sure to add the Intel Logic and Power Group to your LinkedIn groups. Steve Leibson is a Senior Content Manager at Intel. He started his career as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He’s served as Editor in Chief of EDN Magazine and Microprocessor Report and was the founding editor of Wind River’s Embedded Developers Journal. He has extensive design and marketing experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.