Free Webinar: Accelerate FPGA Programming using Data Parallel C++ (DPC++) and the Intel® oneAPI Base Toolkit with the Intel® FPGA Add-on

Are you curious about using Intel® oneAPI and Data Parallel C++ (DPC++) to develop FPGA accelerators? Sign up for this free Webinar that will show you how to use two free tools – the Intel® oneAPI Base Toolkit (Base Kit) and the Intel® FPGA Add-on for the oneAPI Base Toolkit – to speed programming of Intel® FPGAs.

Webinar topics include:

  • How the Intel oneAPI Base Kit enables functional verification through quick emulation and rapid performance tuning
  • How to develop a Hough Transform algorithm, a feature extraction method used in computer vision applications, using DPC++
  • The steps necessary to generate FPGA binaries
  • Using the Intel FPGA Add-on tool to run a pre-compiled bitstream to observe the algorithm’s performance on real FPGA accelerator hardware

 

Register for the Webinar here.

 

For more information about Intel oneAPI and DPC++, see “Springer and Intel publish new book on DPC++ parallel programming, and you can get a free PDF copy!

 

 

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Your costs and results may vary.

© Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others.

 

Published on Categories Acceleration, DPC++, oneAPITags , ,
Steven Leibson

About Steven Leibson

Be sure to add the Intel Logic and Power Group to your LinkedIn groups. Steve Leibson is a Senior Content Manager at Intel. He started his career as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He’s served as Editor in Chief of EDN Magazine and Microprocessor Report and was the founding editor of Wind River’s Embedded Developers Journal. He has extensive design and marketing experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.