Free Webinar: 2nd Generation Intel® Hyperflex™ Architecture Overview for Intel Agilex™ FPGAs. November 7

The 2nd Generation Intel® Hyperflex™ FPGA fabric incorporated into all Intel® Agilex™ FPGAs boosts Fmax by as much as 40% and cuts power by as much as 40%. Now you can attend a free, one-hour Webinar on November 7 that discusses this innovation in FPGA design including an overview of three specific design techniques you can use to take advantage of the Hyper-Registers in the Intel Hyperflex architecture:

  • Hyper-Retiming
  • Hyper-Pipelining
  • Hyper-Optimization

Marlon Price, an Intel Applications Engineer with more than 18 years of FPGA design and instruction experience under his belt, is presenting this Webinar. Price’s specialties include high-end FPGA design optimization, high-speed serial protocols and interfaces, 5G applications, and algorithm acceleration using FPGAs. You are going to want to hear what he has to say.


Click here to register for the 2nd Generation Intel Hyperflex Architecture Webinar.


For more information about the 2nd Generation Intel Hyperflex Architecture, see “2nd Generation Intel® Hyperflex™ FPGA fabric in Intel® Agilex™ FPGAs boosts Fmax by as much as 40% and cuts power, also by as much as 40%.”


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Steven Leibson

About Steven Leibson

Be sure to add the Intel Logic and Power Group to your LinkedIn groups. Steve Leibson is a Senior Content Manager at Intel. He started his career as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He’s served as Editor in Chief of EDN Magazine and Microprocessor Report and was the founding editor of Wind River’s Embedded Developers Journal. He has extensive design and marketing experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.