Free “Office Hours” Live Web session: Getting to Timing Closure Faster with Intel® FPGAs – Tuesday, February 23

Achieving timing closure can be one of the most challenging and perhaps one of the most frustrating facets of FPGA-based design. After performing a complete timing analysis on an FPGA design, getting one or more timing reports indicating a timing failure is an all-too-common occurrence.

How can you fix this problem?

There are many techniques, including:

  • Thorough design analysis to look for common timing failures
  • Adjusting settings and assignments according to tool recommendations
  • Selecting the correct clock resources
  • Adjusting HDL code for optimal performance


Intel® Quartus® Prime Pro development software provides many different tools and reports to help you extract maximum performance from your design. These tools help you achieve faster timing closure.

The upcoming “Office Hours” event on February 23 is devoted to timing closure. It will cover design tips and tricks, but this is not a canned Webcast where information only flows one way. You can also ask specific questions about closing timing on your FPGA designs. This will be an interactive discussion session led by Intel expert who is very familiar with the techniques you can use to achieve timing closure in your FPGA-based designs. No matter what level of experience you have, everyone is welcome to attend to learn and to ask questions.

This session of “Office Hours” will be run by Steven Elzinga. He has worked in the Intel FPGA Training group for nearly four years. Prior to that, he designed video processing cores using FPGAs and got his start in FPGAs as an applications engineer. His current primary focus is timing closure but he also teaches a variety of design classes on a variety of topics ranging from HLS and timing analysis to introductory courses. Elzinga is also a frequent contributor to the Intel community forums.

Come and ask Steve your burning questions about techniques for closing timing faster when designing for Intel FPGAs.

To sign up for this session of Office Hours, click here.


Intel will be holding Office Hours for other topics in the future.  We’d love to hear from you about topics you would like us to cover in the “Office Hours” format.


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Your costs and results may vary.

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Steven Leibson

About Steven Leibson

Be sure to add the Intel Logic and Power Group to your LinkedIn groups. Steve Leibson is a Senior Content Manager at Intel. He started his career as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He’s served as Editor in Chief of EDN Magazine and Microprocessor Report and was the founding editor of Wind River’s Embedded Developers Journal. He has extensive design and marketing experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.