FPGA-based reference design from Algo-Logic and Intel cuts high-speed financial trading latency by 3.8X

Algo-Logic and Intel have developed a high-speed reference framework design that offloads the network stack required for high-speed financial trading to logic instantiated in an Intel® Stratix® 10 FPGA on the Intel® FPGA Programmable Acceleration Card (Intel® FPGA PAC) D5005 platform. The reference design includes:

  • A fast PCIe interface (the Algo-Logic Fast Data Mover)
  • A C/C++ to FPGA business logic implementation area that serves as a target for logic developed using high level synthesis (HLS)
  • A TCP/IP offload engine
  • An ultra-low-latency (ULL) 10GbE media access control (MAC)

According to the conclusion in a new White Paper titled “Low-Latency Data Mover Framework from Algo-Logic with Intel® FPGA PAC D5005,” the reference design achieves 3.8X lower latency compared to a design with just an Ethernet offload engine.1 These innovations significantly accelerate low-latency trading system development while offering the flexibility to add proprietary trading algorithms to the FPGA.

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Notices & Disclaimers

1. Testing by Algo-Logic on October 26, 2020. Server configuration: HPE DL380 G10, CPU = Intel® Xeon® Gold processor 6154 @ 3.00 GHz; DRAM = 128 GB total, and RHEL* 7.6. Production Intel FPGA PAC D5005. For more information, a benchmark report is available under NDA. Contact your sales rep for more information.

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Published on Categories Acceleration, PAC, StratixTags , ,
Steven Leibson

About Steven Leibson

Be sure to add the Intel Logic and Power Group to your LinkedIn groups. Steve Leibson is a Senior Content Manager at Intel. He started his career as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He’s served as Editor in Chief of EDN Magazine and Microprocessor Report and was the founding editor of Wind River’s Embedded Developers Journal. He has extensive design and marketing experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.