Flumaion accelerates quantitative financial calculations for high-frequency trading with Intel® PAC with Intel® Arria® 10 GX FPGA and InAccel Orchestrator

Financial workloads must pore through and process huge data sets. For high-frequency trading and risk management applications, the software demands are both time- and resource-intensive. The computing hardware must keep pace with these demands and must continuously shift industry parameters because financial markets can change direction in an instant. Failure to track a market closely results in expensive trading losses. Hardware accelerators speed algorithm execution and offer significant acceleration for financial applications.

An example financial workload is back testing, which tests a simulated trading series on reliable historical data. Back testing is a computationally intensive task because of the sheer volume of data.

Hardware accelerators based on FPGAs can offer significant performance improvements for financial workloads, which is why Flumaion harnessed the power of the Intel® Programmable Acceleration Card (PAC) with Intel® Arria® 10 GX FPGA to speed quantitative finance applications. Flumaion also employed InAccel’s orchestrator, which enables easy deployment, scaling, resource management, and task scheduling for FPGA-based acceleration of financial applications.

High-level design languages such as OpenCL™, C++, and Data Parallel C++ (part of the Intel® oneAPI initiative) simplify the transition from software programming to FPGA programming. FPGA Acceleration Libraries (FAL) ease a software developer’s FPGA programming experience by providing highly optimized, common functions that are more easily integrated with the developer’s code. The Intel® FAL includes more than 350 functions including linear algebra, statistics, random numbers, date utilities, and options pricing. The Intel FAL also includes pre-compiled FPGA binary files for commonly used financial algorithms such as Black-Scholes, binomial pricing, quadrature integration, partial differential equation solving, and Monte Carlo.

The InAccel Coral manager further abstracts the resources available in a cluster of Intel FPGA PACs, simplifying deployment of one or more applications across multiple FPGAs. InAccel’s manager schedules, dispatches, and manages the accelerated functions. It also balances workloads among the available resources in the Intel FPGA PAC cluster. It manages and configures the accelerator cards as well. InAccel’s orchestrator is fully compatible with the Intel FAL and Intel FPGA PAC cards. InAccel’s repository of precompiled FPGA bitstreams for Intel FPGAs using Intel library functions allows software developers to more easily use hardware accelerators like the Intel® PAC with Intel® Arria® 10 GX FPGA cards.

Flumaion applied its expertise in financial risk analytics, mathematical modeling, and C++ coding experience to harness the performance of the Intel PAC with Intel® Arria® 10 GX FPGA and the productivity enhancements of InAccel tools when developing a quantitative financial modeling testbench. The company then applied a test suite consisting of ten test files to this testbench. Each test file consisted of 3.4 million rows of equity option trades coded in the JSon format. The testbench transforms the JSon files into matrices appropriately formatted for the Intel PAC with Intel® Arria® 10 GX FPGA and then uses the InAccel API to load the matrices into the FPGAs and then to run the workloads.

A new Solution Brief titled “Accelerating Quantitative Finance with FPGA-Based Acceleration Cards” describes the results of these tests, which demonstrate a performance improvement of as much as 3.3X when compared to a system with dual Intel® Xeon® Platinum 8160M processors (24 cores each) running Quantlib.

 

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Notices and Disclaimers

 

The configuration used for both the Quantlib results and the Intel® FAL/InAccel solution comprises Dual Intel® Xeon® Platinum 8160M processors, 384 GB of RAM at 2666 MHz, 375 GB of Intel® Optane™ P4800x persistent memory storage, and two Intel® PAC with Intel® Arria® 10 GX FPGA cards.

Intel® technologies’ features and benefits depend on system configuration and may require enabled hardware, software or service activation. Performance varies depending on system configuration. No computer system can be absolutely secure.

Software and workloads used in performance tests may have been optimized for performance only on Intel® microprocessors.

© Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others.

 

 

Published on Categories Acceleration, PACTags ,
Steven Leibson

About Steven Leibson

Be sure to add the Intel Logic and Power Group to your LinkedIn groups. Steve Leibson is a Senior Content Manager at Intel. He started his career as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He’s served as Editor in Chief of EDN Magazine and Microprocessor Report and was the founding editor of Wind River’s Embedded Developers Journal. He has extensive design and marketing experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.