F5 Networks selected Intel® Stratix® 10 MX FPGAs for its next-gen Application Delivery Controller. Here’s why.

Every year, F5 Networks compiles a survey-driven report on the State of Application Services. This annual report gives us a glimpse of what IT and the networking business will look like over the next year. The report’s first conclusion: 87% of respondents now have multi-cloud architectures, driven by an app-first methodology. Some device, generally a network appliance, needs to accurately and quickly direct the deluge of traffic from the Internet to all of the application servers in those multi-clouds. That appliance is often an Application Delivery Controller (ADC), which is the direct descendant of the network load balancer. First-generation ADCs performed application acceleration and handled load balancing among servers. Current-generation ADCs can handle many more functions and services including SSL Offload, Identity and Access Control, DDoS Protection, Network Firewall, and they can also serve as a Web application firewall.

ADCs are traditionally located in data centers between a firewall (or they are the firewall) and one or more application servers in an area often called the demilitarized zone (DMZ), that part of the enterprise network that sits behind a firewall but outside of or segmented from the internal network. Public servers for Web, mail, and domain services typically reside within the DMZ as well. ADCs in the DMZ provide application access to these public servers.  In situations where the enterprise data center has dissolved in an edgeless multi-cloud, multi-access environment, the ADC and its services still logically exist between the application and its clients.  The ADC is moving with the applications from largely on-premises deployments into additional co-location and public cloud locations.  This is increasing the ADCs value but also presenting it with new use case, deployment, and performance challenges.

F5 makes a variety of networking equipment including ADCs. The company is always developing a new generation of ADCs, which need faster network interfaces, more and faster memory, and generally more programmability with each new generation. F5 has selected the Intel® Stratix® 10 MX FPGA family as the foundation for its next-generation ADC architecture and Tim Michels, Senior Architect at F5 Networks, explains this choice:

“F5 Networks has selected the Intel Stratix 10 MX devices as a key building block in its next generation of hardware-based ADC products. These MX devices create a compelling new mix of logic and memory density, flexible SerDes interfaces via Intel’s EMIB tile technology, access to leading edge DRAM technology with the integrated HBM2 memory stacks, all wrapped up into a single IC package.

The MX devices have allowed the F5 engineering teams to create exceptional value within the prescribed physical, thermal, and cost envelopes required by our target markets and customers.  By sweeping up and removing individual devices from the PCB and collapsing ungainly and difficult parallel buses into efficient and robust SerDes links, Intel has helped F5 maximize its system design density while simultaneously reducing our design cycle times and increasing the quality and reliability of the end result.  At F5 Networks, the standard for system design is the creation of market leading products, and with Intel’s MX devices playing a key role, F5 is meeting that standard.”

Intel Stratix 10 MX FPGAs are truly unique in the industry. Using Intel Embedded Multi-die Interconnect Bridge (EMIB) packaging technology, these FPGAs manage to combine 8 or 16 Gbytes of high-speed HBM2 DRAM, generous chunks of programmable logic and other programmable resources, and SerDes ports that support data rates as fast as 57.8 Gbps using PAM4 signaling into one IC package. The result is significantly better overall system performance and reduced PCB footprint, which explains why F5 selected these versatile devices for their next-generation ADC architecture. These FPGAs hit the sweet spot for high-speed network appliance designs such as ADCs – as well as multi-function accelerators for high performance computing (HPC), data center appliances and other networking equipment, virtual networking function (NFV) accelerators in servers, and broadcast applications. If your next system design needs this kind of performance with these extreme speeds, then you should consider the Intel Stratix 10 MX FPGA family.


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Published on Categories Communications, Networking, StratixTags , ,
Steven Leibson

About Steven Leibson

Be sure to add the Intel Logic and Power Group to your LinkedIn groups. Steve Leibson is a Senior Content Manager at Intel. He started his career as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He’s served as Editor in Chief of EDN Magazine and Microprocessor Report and was the founding editor of Wind River’s Embedded Developers Journal. He has extensive design and marketing experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.