F5 Networks BIG-IP VE for SmartNICs uses Intel® FPGA Programmable Acceleration Card N3000 to efficiently block incoming DDoS attacks in cloud environments while lowering TCO

Tom Atkins, a Product Marketing Manager at F5 Networks, has just published a blog that describes the company’s fully integrated BIG-IP Virtual Edition (VE) solution, which efficiently blocks incoming Distributed Denial of Service (DDoS) attacks in cloud environments using hardware acceleration to realize significant performance and total cost of ownership (TCO) gains. The solution consists of the F5 Networks BIG-IP AFM (Advanced Firewall Manager) Virtual Edition integrated with the Intel® FPGA Programmable Acceleration Card (Intel® FPGA PAC) N3000 SmartNIC. In his blog, Atkins says that the combination of the F5 Networks BIG-IP AFM and the Intel FPGA PAC N3000 SmartNIC frees up CPU cycles for other functions and improves overall DDoS mitigation capacity.

The result: The F5 Networks BIG-IP VE solution can handle DDoS attacks as much as 300X larger than software-only implementations while reducing TCO by approximately 47% by migrating CPU-intensive DDoS mitigation tasks including network threat intelligence, machine learning, packet-based analysis and white listing to the SmartNIC, which frees up high-value CPU cores to run revenue-generating cloud applications instead.

 

For more information, read Atkins’ blog titled “Mitigate DDoS Attacks up to 300x Greater in Magnitude in Cloud Environments: Introducing BIG-IP VE for SmartNICs,” and then watch the associated 10-minute video from F5 Networks titled “Boosting BIG-IP VE Performance with Hardware Acceleration Technologies.” The video features F5 Networks Senior Strategic Architect Jason Rahm, who delves even further into the technical details of this topic.

(Note: In the video, Rahm states that the F5 Networks BIG-IP AFM VE solution with the Intel® FPGA PAC N3000 SmartNIC delivers a 70X performance boost over a software-only implementation, but a footnote in the video’s description states that more recent testing has yielded performance improvements as large as 300X.)

 

Also, please see the associated Solution Brief titled “High Capacity DDoS Protection in Cloud Environments with F5 BIG-IP VE for SmartNICs and Intel FPGA PAC N3000.”

For more information about the Intel FPGA PAC N3000, click here.

 

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Published on Categories Acceleration, Networking, PACTags , ,
Steven Leibson

About Steven Leibson

Be sure to add the Intel Logic and Power Group to your LinkedIn groups. Steve Leibson is a Senior Content Manager at Intel. He started his career as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He’s served as Editor in Chief of EDN Magazine and Microprocessor Report and was the founding editor of Wind River’s Embedded Developers Journal. He has extensive design and marketing experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.