EXOSTIV Labs’ IP and probe module support real-time debugging for Intel® Stratix® 10, Intel® Arria® 10, and Intel® Cyclone® 10 FPGAs

EXOSTIV Labs has developed a high-speed way to get insight into your FPGA-based design so that you can catch design bugs before they escape into production. Most developers use JTAG interfaces when debugging their designs. However, the serial JTAG interface was never intended to be used as a high-speed interface to monitor real-time systems. Even when embedding logic analysis in a design to capture traces, the JTAG interface can represent a real performance bottleneck.

EXOSTIV Labs uses a somewhat different approach that combines as many as sixteen logic-analyzer IP core “capture units” instantiated on the FPGA to monitor as many as 32,768 internal nodes in a design. This IP incorporates triggers like a logic analyzer but uses a high-speed connection to an external probe module to store as much as 8Gbytes of captured data. The ability to monitor so many internal nodes and the agility to move the stored data over high-speed connections to the EXOSTIV probe increase visibility for debugging purposes.

Capture-unit trigger conditions include:

  • Level or transition
  • AND, OR, range conditions
  • Data qualification (data filtering)
  • Sequential triggers in roadmap
  • Concurrent triggering of 1 to 16 capture units
  • Cross-clock domain triggering


The high-speed connection between the FPGA and the EXOSTIV probe module can carry as much as 50 Gbps worth of data from the FPGA to the probe module, as shown in Figure 1.


Figure 1: EXOSTIV IP in an FPGA communicates with an external probe module at speeds as fast as 50 Gbps to capture real-time debugging data.


Currently, the EXOSTIV IP and probe are compatible with Intel® Stratix® 10, Intel Arria® 10, and Intel Cyclone® 10 FPGAs and the EXOSTIV software is compatible with the Intel® Quartus® Prime Software Suite. EXOSTIV offers an EP6000 probe, which operates at a maximum of 6.6 Gbps per channel, and the EP12000 probe, which operates at a maximum of 12.5 Gbps per channel. Both probes are available in 1-, 2-, and 4-channel versions.

Here’s a video demo of the EXOSTIV system operating with an Intel Stratix 10 GX FPGA development card. The FPGA card connects to the EXOSTIV probe module over a QSFP+ connection:



For more information about these EXOSTIV development tools, please contact EXOSTIV directly.


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Published on Categories Arria, Cyclone, StratixTags , ,
Steven Leibson

About Steven Leibson

Be sure to add the Intel Logic and Power Group to your LinkedIn groups. Steve Leibson is a Senior Content Manager at Intel. He started his career as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He’s served as Editor in Chief of EDN Magazine and Microprocessor Report and was the founding editor of Wind River’s Embedded Developers Journal. He has extensive design and marketing experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.