EEJournal’s Kevin Morris weighs in on ZTE’s selection of Intel® eASIC™ devices for 5G wireless upgrade


On May 1, Intel announced that ZTE had selected Intel® eASIC™ devices for its 5G wireless products to meet the critical cost and power requirements demanded by large-scale 5G deployments. (See “ZTE Selects Intel’s eASIC Devices for 5G Wireless Deployment.”) A week later, EEJournal’s founder and Editor-in-Chief Kevin Morris weighed in on the announcement in his article titled “eASIC’s Big Win: Intel’s Acquisition Finds Its New Legs.” After spending four long paragraphs on the history of structured ASICs, Morris writes:

“The cool thing about structured ASIC as implemented by eASIC is the smooth transition from an FPGA design to a functionally equivalent ASIC.”

Why transition at all? Here’s Morris’s cogent explanation:

“…a substantial percentage of the FPGA chips sold have been in rapidly evolving application areas where unit cost and power consumption are less important than getting your box in customers’ hands right now – instead of 12 to 18 months from now. This is critical with technologies such as 5G, for example, where putting working gear into customers’ hands is vastly more valuable than cutting big swaths out of the BOM cost.”

Eventually, when designs become more stable, as they often do, there’s an opportunity to reduce costs with optimized, custom silicon. Morris discusses this situation in his article:

“It would be premature to start developing a full-blown ASIC before the technology and standards stabilize. That’s one of the big reasons for using FPGAs in the first place. Once the technology does stabilize, however, the race is on once again. The first company to deliver cost-reduced, speed- and power-optimized non-FPGA versions of their gear to market will capture the high-margin, high-volume sweet spot of the mass adoption cycle…

“If you start developing a conventional ASIC on day zero of stable technology standards and specs, you’re a good two years from launching second-generation products. But, if you could just take your FPGA design and magically morph it into an ASIC with most of the benefits of a full-blown scratch ASIC design, you could beat all those conventional-ASIC folks by a meaningful margin.”

Morris then concludes his article with a bit more analysis:

“A second fun fact can be divined by looking at eASIC’s history. It turns out that the company has a robust design flow for converting designs from [competitive] FPGAs as well. This gives Intel a… second shot at capturing the high-volume phase of a design, even if they lost out to [the competition] on the initial FPGA-based version.”


Be sure to read the full article on the EEJournal site.

Published on Categories 5G, Communications, eASICTags , ,
Steven Leibson

About Steven Leibson

Be sure to add the Intel Logic and Power Group to your LinkedIn groups. Steve Leibson is a Senior Content Manager at Intel. He started his career as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He’s served as Editor in Chief of EDN Magazine and Microprocessor Report and was the founding editor of Wind River’s Embedded Developers Journal. He has extensive design and marketing experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.