Develop custom 200 Gbps packet-processing pipelines using Netcope P4 for SmartNICs based on Intel® Stratix® 10 FPGAs


P4 is the latest high-level programming language for network packet-processing, data-plane pipeline development and FPGAs make excellent, high-performance targets for executing compiled P4 programs. P4 is an open-source, permissively licensed language maintained by the non-profit P4 Language Consortium. Netcope has just upgraded its cloud-based P4 compiler so that it is now capable of generating netlists for Intel® Stratix® 10 FPGAs. The resulting pipelines can handle 200 Gbps network traffic. (The Netcope P4 compiler was already capable of generating netlists for Intel Arria® 10 FPGAs.)

Using P4, networking equipment architects can create high-speed, packet-processing pipelines even if they’re not experts or even familiar with FPGA-based design. Even experienced FPGA users will realize a productivity increase when developing packet-processing pipelines using P4.

The Netcope P4 cloud-based service manages the entire end-to-end process of transforming a P4 description into an FPGA bitstream. While P4 was originally developed to create network switches, the language is very adaptable and can be used to develop related portions of the network infrastructure that can benefit from the P4 language’s parsing, filtering, packet-counting, and load-balancing capabilities. P4 can be used to develop a variety of packet-processing pipelines for:

  • In-band telemetry
  • Accelerated, high-speed virtual network switches
  • Network traffic preprocessors
  • Segment routing
  • Load balancing
  • SDN/NFV acceleration


Here’s a video describing the Netcope P4 compiler:



For additional information about the Netcope’s P4 compiler, click here.

Published on Categories 5G, Communications, Networking, P4, StratixTags , , , ,
Steven Leibson

About Steven Leibson

Be sure to add the Intel Logic and Power Group to your LinkedIn groups. Steve Leibson is a Senior Content Manager at Intel. He started his career as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He’s served as Editor in Chief of EDN Magazine and Microprocessor Report and was the founding editor of Wind River’s Embedded Developers Journal. He has extensive design and marketing experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.