Data processing tests by NTT Data suggest that an Intel® FPGA PAC can filter, aggregate, sort, and convert files 4x faster than software alone

Nearly 80% of total data processing time is spent on tasks such as filtering, aggregation, sorting, and format conversion. NTT Data conducted proof-of-concept tests aimed at improving data processing performance for these tasks. The tests employed an Intel® FPGA Programmable Acceleration Card (Intel® FPGA PAC) to process Linux audit logs, resulting in processing speeds more than four times faster than the same processing done in exclusively in software.

Two factors drove this exercise:

  1. The advent of Intel FPGA PACs and other associated technologies have now made it far easier for companies to incorporate FPGAs as processing elements in data center servers.
  2. HLS technology—which enables engineers to use programming languages with C-like syntaxes for application development targeting FPGAs—makes it easier for software engineers to develop applications that target FPGAs.

Performance improvements enabled by FPGA processing have two key benefits in the data center:

  1. Fewer Servers. FPGA processing improves each server’s processing capacity and thus reduces the number of servers needed for a given task. Server aggregation reduces hardware acquisition and construction costs and lowers running costs, which include operation, maintenance, space, and power.
  2. Reduced cloud instance usage time. Customers are charged by the processing time used in a cloud environment so shortening processing time reduces user costs and makes cloud services more economically attractive to end users.

A new six-page White Paper titled “Effective Use of FPGAs for Data Utilization” provides extensive technical details and discussions, results, and test conditions for these NTT Data acceleration tests. Click here to download the White Paper.

 

For more information about application acceleration for Intel® Xeon® CPUs with FPGAs in the data center, see the Intel® FPGA Acceleration Hub.

 

 

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Published on Categories Acceleration, Cloud, PACTags , ,
Steven Leibson

About Steven Leibson

Be sure to add the Intel Logic and Power Group to your LinkedIn groups. Steve Leibson is a Senior Content Manager at Intel. He started his career as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He’s served as Editor in Chief of EDN Magazine and Microprocessor Report and was the founding editor of Wind River’s Embedded Developers Journal. He has extensive design and marketing experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.