CXL Consortium incorporates – Just ahead: high-speed, coherent interconnect for accelerators and memory based on PCIe 5.0

The Compute Express Link (CXL) Consortium announced its incorporation this month. The consortium’s founding members (Alibaba, Cisco, Dell EMC, Facebook, Google, Hewlett Packard Enterprise, Huawei, Intel Corporation and Microsoft) jointly made the announcement. CXL is a new high-speed CPU-to-Device and CPU-to-Memory interconnect designed to accelerate next-generation data center performance. It’s is an open, industry-standard interconnect that offers high-bandwidth, low-latency connectivity between host processor(s) and other devices such as accelerators, memory buffers, and smart I/O devices.

There are currently more than 65 member companies in the CXL Consortium, indicating that the CXL specification has some significant momentum. Intel spent four years developing the CXL specification. Intel and the eight other founding members announced the initial establishment of the CXL Consortium in March of this year. The CXL 1.1 specification is already available for download (see below).

CXL is based on the PCIe 5.0 specification’s physical layer infrastructure and is designed to address the demanding needs of high-performance computational workloads by supporting coherent communications among CPUs, accelerators, and memory for heterogeneous processing and memory systems. Some of the many applications suited to CXL foundational technology include artificial intelligence and machine learning (AI/ML), communications and networking systems, and high-performance computing (HPC).

Intel announced its first CXL-capable FPGAs, the 10 nm Intel® Agilex™ FPGA family, back in April of this year. (See “How do the new Intel Agilex FPGA family and the CXL coherent interconnect fabric intersect?”) For more information about the Intel Agilex FPGA family and early recipients of these devices, see “Intel Driving Data-Centric World with New 10nm Intel Agilex FPGA Family” and  “First Shipments of 10nm Intel® Agilex™ FPGAs reach early access customers.”

 

The CXL 1.1 specification is now available for download here.

A White Paper describing the CXL technology is available here.

 

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Published on Categories Agilex, AI/ML, Communications, CXL, HPC, NetworkingTags , , , , ,
Steven Leibson

About Steven Leibson

Be sure to add the Intel Logic and Power Group to your LinkedIn groups. Steve Leibson is a Senior Content Manager at Intel. He started his career as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He’s served as Editor in Chief of EDN Magazine and Microprocessor Report and was the founding editor of Wind River’s Embedded Developers Journal. He has extensive design and marketing experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.