Colorado Engineering Inc plans lower-cost PCIe development platform based on Intel® Agilex™ FPGAs

Platinum Intel Design Solutions Network member Colorado Engineering Inc (CEI) is one of the companies that’s receiving early samples of the new Intel® Agilex™ FPGA, per last week’s announcement. CEI’s headquarters overlooks Garden of the Gods park in Colorado Springs. The company has created more than fifty FPGA-based designs for a variety of clients and has been working with Intel and Altera (before Intel purchased Altera) as a design services provider since 2003. Principals working at the company including Dr. Larry Scally – the company’s co-founder, President, and CTO – have deep experience in FPGA-based design that stretches back to the 1980s.

CEI has focused on serving the military and aerospace sector but has expanded to other markets such as computing and storage, test and measurement, software-defined radio (SDR), and 5G fronthaul applications. Any analog or digital application that requires high-speed, high-performance processing, and turnkey design solutions is a CEI opportunity.

For example, CEI developed a mixed-signal processing board called the Peregrine II Digital Receiver/Exciter (DREX) for Intel. The board targets 5G SDR applications. It incorporates five Intel Stratix® 10 GX FPGAs and an Intel Core i7™ processor mounted on a single-board computer (SBC) module that plugs into a COM Express site on the board (see Figure 1).

 

Figure 1. The CEI Peregrine II Digital Receiver/Exciter (DREX) board incorporates five Intel Stratix 10 GX FPGAs (center) and a COM Express site (lower right) that accepts an SBC module based on an Intel Core i7 processor.

 

CEI developed the 10,000-component Peregrine II board in just six months to meet a very tight deadline; it needed to be ready for Mobile World Congress in 2016. The Intel Core™ i7 processor on the COM Express SBC and the five Intel Stratix 10 GX FPGAs allow CEI’s Peregrine II Digital Receiver/Exciter (DREX) to deliver 50 TFLOPS of processing power in a 10×16 inch package. The board is designed for 5G SDR applications and therefore incorporates four, 12 bit, 2.5 Gsamples/sec ADC channels and four, 12 bit, 5.7 Gsamples/sec DAC channels. The Intel Stratix 10 FPGAs communicate with the ADCs and DACs using JESD204B and LVDS interfaces respectively.

CEI has very specific plans for its early access Intel Agilex FPGAs. The company plans to develop a lower-cost, high-performance PCIe development board around this device. (Note: The Intel Agilex FPGA has PCIe Gen5 interface ports.) CEI also plans to develop appropriate host drivers, specific algorithms, and other associated IP for the board to create a turnkey development platform for designers who want to start creating designs based on the Intel Agilex FPGA without first designing a development board.

For more information about CEI’s Peregrine II development platform or the upcoming development platform based on the Intel Agilex Stratix 10 FPGAs, please contact CEI directly.

 

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Published on Categories 5G, Acceleration, Agilex, Cloud, Storage, StratixTags , , , ,
Steven Leibson

About Steven Leibson

Be sure to add the Intel Logic and Power Group to your LinkedIn groups. Steve Leibson is a Senior Content Manager at Intel. He started his career as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He’s served as Editor in Chief of EDN Magazine and Microprocessor Report and was the founding editor of Wind River’s Embedded Developers Journal. He has extensive design and marketing experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.