Chiplets (tiles) create a high-speed path for getting new FPGAs to market


These days, trade publications routinely publish articles about chiplets and related technologies. For example, on June 20, Mark LaPedus published an article on the Web site titled “What’s Next In Advanced Packaging” that said:


“While scaling remains an option for new designs, the industry is searching for alternatives. Another way to get the benefits of scaling is by putting multiple and advanced chips in an advanced package, also known as heterogeneous integration.”


Heterogeneous integration allows a semiconductor manufacturer to construct ICs using various die that have been fabricated with different process technologies. Die that are designed to be assembled and connected together in one package are commonly called chiplets. Previously, these chiplets might have been packaged individually and connected together on a PCB. However, using direct die-to-die interconnect within one package allows the packaged device to run at much faster speeds due to significantly lower trace impedances within the IC package.

Intel developed Embedded Multi-die Interconnect Bridge (EMIB) technology several years ago to enable heterogeneous integration and the technology has proven essential to the rapid development and proliferation of the latest Intel FPGAs. All members of the Intel Stratix 10 GX, SX, TX, and MX FPGA and SOC FPGA families employ heterogeneous integration and chiplets (which Intel calls “tiles”) and the recently announced Intel® Agilex™ FPGA family similarly leverages EMIB and chiplet technologies. In fact, various members in the Intel Agilex FPGA family will incorporate some of the very same tiles used to fabricate Intel® Stratix® 10 TX FPGAs. Of course, Intel will be creating new tiles for the Intel Agilex FPGA family as well.

The interconnection technologies used to carry signals from one chiplet to another are quite important for successful heterogeneous integration. On June 18, Dylan McGrath published an article titled “Chiplet Ecosystem Slowly Picks up Steam” on the EETimes Web Site. In that article, McGrath discusses the Open computer Project’s Open Domain-Specific Architecture (ODSA) group, which defining an open interface standard for chiplet-based design. The article also reports that Intel released “version 5.2 of PHY Interface for PCI Express (PIPE), a stripped-down version of the PCI Express interface that is described as a configurable short-reach PHY,” to be used for heterogeneous integration.

Previously, Intel released its AIB protocol, used by Intel for heterogeneous integration of many production devices including Intel Stratix 10 FPGAs, through the DARPA Common Heterogeneous Integration and IP Reuse Strategies (CHIPS) program. (See “Intel releases Royalty-Free, High-Performance AIB Interconnect Standard to Spur Industry’s Chiplet Adoption and Grow the Ecosystem.”)

Chiplets permit a divide-and-conquer design strategy for IC designers. Some portions of an IC need the very best that Moore’s Law can deliver in terms of on-chip device density. FPGA logic and FPGA interconnect fabric arrays fall into this category. However, Moore’s-Law scaling simply doesn’t work for every function on a chip, not any more. In particular, I/O functions that must drive off-chip signals need larger transistors to drive the larger off-chip load impedances. However, I/O functions are well-suited to implementation using chiplets or, in Intel’s case, tiles.

Figures 1 through 4 illustrate the product flexibility that Intel’s EMIB and tiles make possible for the Intel Stratix 10 device family. All of the Intel Stratix 10 TX family members shown in these four figures employ the same relatively small set of FPGA fabric die, shown in blue in the center of each figure, but the entire family is much larger and more capable thanks to the use of various and a varied number of tiles to greatly enhance these devices’ I/O features and capabilities. As Figure 1 through 4 show, the FPGA fabric die in the Intel Stratix 10 device family are attached via Intel’s EMIB technology to between two and six interface tiles to create the final packaged product. (The maximum number of tiles currently supported is six per FPGA die.)


Figure 1: Intel Stratix 10 TX with two tiles.


Figure 2: Intel Stratix 10 TX with three tiles.



Figure 3: Intel Stratix 10 TX with four tiles.


Figure 4: Intel Stratix 10 TX with six tiles.


The tiles also vary in capabilities. For example, an H-tile has a total of twenty-four serial channels, which can all be configured as GX channels or as a combination of GX and (as many as sixteen) GXT channels, as long as the total number of channels does not exceed 24. The GX transceiver channels in Intel Stratix 10 devices support data rates to 17.4 Gbps. Depending on the tile used GXT transceiver channels in Intel Stratix 10 devices support data rates to 28.3 Gbps. (For more information about these Intel Stratix 10 transceiver channels, see the “Intel Stratix 10 L- and H-Tile Transceiver PHY User Guide.”

An E-tile implements twenty-four GXE NRZ serial channels capable of operating at line rates as fast as 28.9 Gbps. Alternatively, the E-tile can be configured as twelve PAM4 serial channels capable of operating at line rates as fast as 57.8 Gbps. That means that an Intel Stratix 10 TX device with five E-tiles can be configured with nearly 3.5 Tbps of serial I/O capability for both input and output. That’s a significant amount of I/O bandwidth, capable of supporting as many as eight 400 Gbps Ethernet ports.

However, not all designs based on Intel Stratix 10 TX FPGAs will need such a large amount of I/O bandwidth, so the use of tiles and EMIB to create multiple device variants with varying amounts of I/O ports allowed Intel to quickly create a large device family. Similarly, the recently announced Intel Agilex FPGA family (see “Intel Driving Data-Centric World with New 10nm Intel Agilex FPGA Family”) relies on the flexibility and other advantages of a tile-based design approach, as illustrated in Figure 5.


Figure 5: Intel Agilex FPGAs also leverage a tile-based design philosophy and Intel EMIB technology.


Tiles (or chiplets) give Intel the ability to reuse proven I/O silicon for Intel Agilex devices, which will utilize some of the same tiles that are available in Intel Stratix 10 FPGAs. One such example: the E-tile, which is the same tile used to fabricate some Intel Stratix 10 FPGAs. In addition, Intel will be developing new tiles. Because it’s much easier to design, fabricate, and test a tile rather than an entire FPGA IC, tiles also give Intel an express lane to get new products to market faster.

FPGA users also get advantages from Intel’s use of tiles. First, assuming they’ve previously worked with Intel Stratix 10 devices, these users will already have designed with and will be familiar with the I/O characteristics of the E-tile’s serial transceivers. They will also be familiar with programming these transceivers for various serial I/O protocols, which should provide a nice productivity boost to design projects based on Intel Agilex devices. Second, FPGA users will be able to more quickly reap benefits from the new tile-based features in any future Intel Agilex FPGA devices as Intel develops them and brings them to market.

Stay tuned.


For more information about the use of tiles in Intel Agilex FPGAs, please see “Intel Agilex FPGAs Deliver a Game Changing Combination for the Data Centric World.”

Published on Categories Agilex, Chiplets, EMIB, Stratix, TilesTags
Steven Leibson

About Steven Leibson

Be sure to add the Intel Logic and Power Group to your LinkedIn groups. Steve Leibson is a Senior Content Manager at Intel. He started his career as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He’s served as Editor in Chief of EDN Magazine and Microprocessor Report and was the founding editor of Wind River’s Embedded Developers Journal. He has extensive design and marketing experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.