Category: Acceleration

• Low-latency key-value store resides in FPGA SRAM, delivers data in a deterministic 500 nsec Professor John Lockwood sits behind the wheel, piloting his slick electric roadster around a landscape filled with renewable energy sources: wind turbines, solar arrays, and a hydroelectric dam. He’s actually sitting at a simulation console in the Algo-Logic booth at the Supercomputing 2019 (SC’19) conference in the Denver Convention Center, watching the simulated world go by on a large-screen monitor...
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• Levyx Xenon Acceleration Framework runs on Intel® Xeon® CPUs, Intel® Optane™ SSDs, and FPGA-based Intel® programmable accelerator cards, speeds HFT model backtesting Backtesting seeks to estimate the real-world performance of specific high-frequency trading (HFT) strategies or models as if they had been employed during a previous trading period. Levyx developed its hardware-accelerated Risk Analytics Acceleration Framework to help customers realize more profit from an HFT financial model by speeding up the calculations associated with that trading model. Backtesting these HFT financial models...
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• Register for Intel® oneAPI Programming Workshops and an FPGA-specific oneAPI Lunch & Learn session next week at SC’19 in Denver Last June, Intel’s engineering leaders provided an update on Intel’s software project – “One API” – which delivers a unified programming model that allows you to optimize performance for a wide range of data-centric workloads across scalar, vector, matrix and spatial architectures deployed in CPU, GPU, AI, FPGA and other accelerators. (See “Intel’s ‘One API’ Project Delivers Unified Programming Model...
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• Altran demonstrates FPGA-based Fronthaul Gateway software framework for 5G at Mobile World Congress Los Angeles Last week, at Mobile World Congress Los Angeles, Altran demonstrated its disaggregated Fronthaul Gateway software framework for mobile communications networks based, in part, on Intel FPGAs. This software framework allows wireless carriers, network equipment manufacturers (NEMs), and network equipment providers (NEPs) to accelerate large-scale 5G fronthaul deployment in a scalable manner. With 5G technology now driving growth in mobile networking,...
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• Corning Announces 5G In-Building Network Collaboration with Intel using Intel® Xeon® Scalable processors, Intel® FlexRAN Reference Architecture, and Intel® FPGA PAC N3000 Yesterday, Corning announced a collaborative effort with Intel to accelerate the availability of 5G communications within buildings. The collaboration will ultimately deliver a virtual platform for Corning’s 5G network solutions powered by Intel® Xeon® Scalable processors, based on the Intel® FlexRAN Reference Software Architecture, and incorporating the Intel® FPGA Programmable Acceleration Card (PAC) N3000 and 10/25/40Gb Intel® Ethernet 700 Series...
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• Free Webinar: Accelerate Cassandra NoSQL Database Performance using Intel® FPGA Programmable Acceleration Cards rENIAC’s Distributed Data Engine accelerates Apache Cassandra NoSQL database performance by as much as an order of magnitude. It improves both throughput and latency for database transactions. Facebook originally developed the Apache Cassandra distributed NoSQL database to power its inbox search feature and released it to the open-source community more than a decade ago, where it has continued to flourish....
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• New White Paper describes high-performance Next-Generation Core Networks Proof of Concept with FPGA-based NFV acceleration Intel, Affirmed Networks, and Dell EMC describe a proof of concept for high-performance Next-Generation Core Networks (NGCN) in a new White Paper titled “Enabling Communications Service Providers to Meet 5G High Density I/O Goals through Software Optimization and Hardware Acceleration.” This White Paper describes a state-of-the-art solution for a commercial, standalone 5G core network (5GCN) that delivers 100 Gbps/CPU socket...
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• Handle one million IPSec SAs at 100 Gbps using Arrive Technologies’ IPSec core and the Intel® FPGA PAC N3000 card Arrive Technologies’ FPGA-accelerated IP security (IPSec) IP core, optimized for the Intel® FPGA Programmable Acceleration Card (PAC) N3000, delivers wire-speed cryptographic processing (including AES-GCM (128/192/256), AES-CBC (128/192/256), SHA-1/2, and others) at Ethernet rates as fast as 100 Gbps while handling as many as one million Security Associations (SAs). With this sort of performance, Arrive’s IPSec solution based on the Intel...
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• Network service providers and operators can serve many more customers with better throughput, lower TCO using Benu Networks’ vBNG with FPGA-based VNF acceleration Network service providers and network operators perpetually face the challenge of reducing the costs associated with service delivery while also finding cost-effective ways to expand into new markets and serve an ever-growing number of subscribers while tailoring these services on a per-subscriber basis. Meeting these challenges requires a different approach and Benu Networks’ different approach relies heavily upon virtual network...
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• Free Intel and Napatech Webinar: Can Your Network Respond Quickly Enough to Defend Against Cyber Attacks? Corporate data breaches cost many millions of dollars and they’re becoming more frequent as faster line rates make it easier for cybercriminals and other malicious actors to penetrate corporate and government networks with the intent of causing harm. Consequently, commercial firms, governments, and other entities are beefing up their network security. Network security hardware and software has developed on two...
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