Category: Acceleration

• Megh Computing demos advanced, scalable Video Analytics Solution portfolio at WWT’s Advanced Technology Center Megh Computing’s Video Analytics Solution (VAS) portfolio implements a flexible and scalable video analytics pipeline consisting of the following elements: Video Ingestion Video Transformation Object Detection and Inference Video Analytics Visualization   Because Megh’s VAS is scalable, it can handle real-time video streams from a few to more than 150 video cameras. Because it’s flexible, you can use the VAS...
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• BittWare announces IA-420F PCIe accelerator card and IA-220-U2 computational storage accelerator based on Intel® Agilex™ FPGAs and SoC FPGAs BittWare has added two new accelerator products based on Intel® Agilex™ FPGAs and SoC FPGAs to the previously announced IA-840F Enterprise-Class FPGA Accelerator. (See “BittWare IA-840F FPGA Accelerator PCIe Card bristles with high-speed I/O, is based on an Intel® Agilex™ FPGA.”) The new IA-420F half-height, half-length, single-width PCIe card with multiple 100G network ports is designed for SmartNIC and computational...
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• Intel at MWC: Panel Discusses “How is the O-RU reference architecture driving 5G Radio Development?” Telecom operators need to reduce development time and while implementing new solutions to increase the performance and reliability of 5G networks in a cost-effective manner. Operators have already implemented open systems in their network cores and virtualizing functions, and now they want to achieve the same benefits with RANs including Radio Units (RUs). The Open RU (O-RU) roadmap covers both...
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• Intel® Agilex™ FPGAs with high-performance Crypto Blocks target Infrastructure Processing Units (IPUs), SmartNICs, and 5G Networks From the edge to the cloud, security challenges in the form of cyberattacks and data breaches loom ever larger as attacks on high-speed networks multiply. Massive amounts of data are at risk but so are physical resources including critical physical infrastructure. Cryptography and authentication represent potent countermeasures to these attacks. The latest members of the Intel® Agilex™ FPGA and SoC...
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• Principal Industry Analyst Patrick Moorhead Explores Infrastructure Processing Units (IPUs) on Forbes.com Navin Shenoy, Executive VP and GM for the Data Platforms Group at Intel, presented a vision for Infrastructure Processing Units (IPUs) earlier this week in a keynote speech titled "Why You Have Been Thinking About the Future of the Data Center All Wrong" at The Six Five Summit, a strategy event presented by Patrick Moorhead’s company, Moor Insights & Strategy,...
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• Want to know more about how Infrastructure Processing Units (IPUs) are revolutionizing data center architecture? A 4-minute video provides clarity Yesterday, Intel unveiled its vision for infrastructure processing units (IPUs), programmable networking devices that free up CPU cycles by taking over and intelligently managing system-level infrastructure in data centers. (See “Infrastructure Processing Units (IPUs) intelligently manage and accelerate data center infrastructure.”) The company also announced that IPUs based on Intel® CPUs and Intel® FPGAs are already shipping from Intel and...
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• Infrastructure Processing Units (IPUs) intelligently manage and accelerate data center infrastructure Today during the virtual Six Five Summit, Intel unveiled its vision for infrastructure processing units (IPUs), programmable networking devices designed to enable cloud and communication service providers (CSPs and CoSPs) to reduce overhead and free up CPU cycles by taking over and intelligently managing system-level infrastructure in data centers. IPUs help data centers better utilize resources by providing a secure,...
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• Learn to use Data Parallel C++ to accelerate MapReduce processing at this ISC oneAPI Dev Summit session on June 23 Many workloads have inherent data parallelism which can be leveraged to achieve optimal performance. However, it is challenging to design data parallel programs and map them to different hardware targets. Data Parallel C++ (DPC++) is an open alternative for cross-architecture development, aiming to address this challenge. A session titled “Word-Count with MapReduce on FPGA, A DPC++ Example” at the upcoming...
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• Can FPGAs outperform GPUs for some AI workloads? Answer: Yes For many AI workloads, it can be challenging to achieve the full compute capacity reported by GPU vendors. Even for highly parallel computation such as general matrix multiplication (GEMM), GPUs can only achieve high utilization at certain large matrix sizes. FPGAs offer a different approach to AI-optimized hardware. Unlike GPUs, FPGAs offer unique fine-grained spatial reconfigurability where the output of...
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• Free Webinar: Using Intel® oneAPI™ to Achieve High-Performance Compute Acceleration with FPGAs Interested in learning how to use the Intel® oneAPI™ open, unified programming model to accelerate data-centric workloads using FPGAs? Then sign up for the free Webinar titled “Using Intel oneAPI to Achieve High-Performance Compute Acceleration with FPGAs.” It’s being presented on March 23 and March 25 by Intel and Bittware. The Webinar will zero in a real-world, 2D FFT workload...
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