Can FPGAs outperform GPUs for some AI workloads? Answer: Yes

For many AI workloads, it can be challenging to achieve the full compute capacity reported by GPU vendors. Even for highly parallel computation such as general matrix multiplication (GEMM), GPUs can only achieve high utilization at certain large matrix sizes. FPGAs offer a different approach to AI-optimized hardware.

Unlike GPUs, FPGAs offer unique fine-grained spatial reconfigurability where the output of each function can be routed directly to the input of the function that needs it. This approach allows greater flexibility to accommodate specific AI algorithms and application characteristics that enable improved utilization of available FPGA compute capabilities and, therefore, improved performance. Specialized soft processors, also called overlays, allow FPGA programming in a fashion similar to processors, where the FPGA programming is done purely via software toolchains. This programming approach abstracts away FPGA-specific hardware complexity.

A new White Paper titled “Real Performance of FPGAs Tops GPUs in the Race to Accelerate AI” presents the first performance evaluation of the new Intel® Stratix® 10 NX FPGA in comparison to the Nvidia T4 and V100 GPUs. This performance evaluation was conducted over a suite of real-time inference workloads, based on results published in a paper presented at the 2020 IEEE International Conference on Field Programmable Technology. The workloads for the FPGA were deployed using an implementation of a soft AI processor overlay called the Neural Processing Unit (NPU) with a tool chain that enables software-centric FPGA programming without invoking FPGA-specific hardware EDA tools.

Results show that the Intel Stratix 10 NX FPGA achieves far better utilization and performance than the tested GPUs for these AI workloads. Want the details? Click here to download the White Paper.

 

 

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Published on Categories Acceleration, AI/ML, StratixTags , ,
Steven Leibson

About Steven Leibson

Be sure to add the Intel Logic and Power Group to your LinkedIn groups. Steve Leibson is a Senior Content Manager at Intel. He started his career as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He’s served as Editor in Chief of EDN Magazine and Microprocessor Report and was the founding editor of Wind River’s Embedded Developers Journal. He has extensive design and marketing experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.