Build efficient 5G and 4G telecom offload functions quickly using Netcope Technologies’ P4 service and Intel® FPGA Programmable Acceleration Cards

Smart Network Interface Cards (SmartNICs) can boost performance in mobile telecom networks. For 4G networks, SmartNICs can be used to implement many network functions in virtual machines or containers rather than using dedicated hardware, resulting in better performance and more network flexibility. Meanwhile, 5G networks will demand even more performance and flexibility, and SmartNICs can meet these goals. An Intel® FPGA Programmable Acceleration Card (PAC) N3000 – a full-duplex 100 Gbps in-system re-programmable acceleration card for multi-workload networking application acceleration – can offload telecom network server CPUs, which reduces the total number of required servers and cuts both capital and operational expenses.

A new Intel White Paper titled “Making Virtualized Mobile Gateways More Efficient,” written in conjunction with Netcope Technologies – a Gold member of the Intel® FPGA Partner Program – discusses the use of the open-source P4 network programming language in conjunction with Netcope’s P4 service to quickly develop and deploy offload cores that accelerate networking functions.

The offloaded networking functions are often straightforward but require significant compute performance, which makes them ideal for conversion to an FPGA-based IP core using the P4 language. Examples of such functions include Network Address Translation (NAT), Deep Packet Inspection (DPI), and content-specific processing optimizations for Web and video traffic. Using P4 to describe these functions rather than traditional FPGA programming languages including VHDL and Verilog can reduce development time for these functions from weeks to days. In addition, FPGA-specific design knowledge is often not required to develop these functions using P4.

For more details, click here to download this new Intel White Paper.

 

For more information about the Netcope implementation of P4 used with Intel® FPGAs, see “Develop custom 200 Gbps packet-processing pipelines using Netcope P4 for SmartNICs based on Intel® Stratix® 10 FPGAs.”

 

 

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Steven Leibson

About Steven Leibson

Be sure to add the Intel Logic and Power Group to your LinkedIn groups. Steve Leibson is a Senior Content Manager at Intel. He started his career as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He’s served as Editor in Chief of EDN Magazine and Microprocessor Report and was the founding editor of Wind River’s Embedded Developers Journal. He has extensive design and marketing experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.