BittWare’s 520NX Accelerator Card harnesses AI-optimized power of the Intel® Stratix® 10 NX FPGA

BittWare has just announced the 520NX AI Accelerator PCIe card based on the AI-optimized Intel® Stratix® 10 NX FPGA, which incorporates specialized AI Tensor blocks with a theoretical peak computational speed of 143 INT8 TOPS and 8 Gbytes of in-package, stacked high-bandwidth memory (HBM2). In addition to the Intel Stratix 10 NX FPGA’s internal resources, the 520NX AI Accelerator card’s on-board resources include a PCIe Gen3 x16 host interface, four independently clocked QSFP28 card cages that support as many as four 100G optical transceiver modules, and two DIMM sockets that can accommodate as much as 256 Gbytes of memory.

The 520NX offers enterprise-class features and capabilities for application development and deployment including:

  • HDL developer toolkit: API, PCIe drivers, application example designs, and diagnostic self-test
  • Passive, active, or liquid cooling options
  • Multiple OCuLink expansion ports for additional PCIe, storage, or network I/O

 

The BittWare 520NX AI Accelerator card based on the AI-optimized Intel Stratix 10 NX FPGA

 

The Intel Stratix 10 NX FPGA was introduced earlier this year. (See “Intel has just announced its first AI-optimized FPGA – the Intel® Stratix® 10 NX FPGA – to address the rapid increase in AI model complexity.”) More recently, the FPGA’s AI capabilities have been demonstrated by Myrtle.ai, running a WaveNet text-to-speech application that can synthesize 256 simultaneous streams of 16 kbps audio. (See “WaveNet Neural Network runs on Intel® Stratix® 10 NX FPGA, synthesizes 256 16 kHz audio streams in real time.”) The new BittWare 520NX AI Accelerator card makes it much easier to develop applications based on the Intel Stratix 10 NX FPGA by providing the FPGA on a proven, ready-to-integrate PCIe card.

For more information about the 520NX AI Accelerator card, please contact BittWare directly.

 

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Published on Categories Acceleration, AI/ML, StratixTags , ,
Steven Leibson

About Steven Leibson

Be sure to add the Intel Logic and Power Group to your LinkedIn groups. Steve Leibson is a Senior Content Manager at Intel. He started his career as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He’s served as Editor in Chief of EDN Magazine and Microprocessor Report and was the founding editor of Wind River’s Embedded Developers Journal. He has extensive design and marketing experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.