BittWare announces IA-420F PCIe accelerator card and IA-220-U2 computational storage accelerator based on Intel® Agilex™ FPGAs and SoC FPGAs

BittWare has added two new accelerator products based on Intel® Agilex™ FPGAs and SoC FPGAs to the previously announced IA-840F Enterprise-Class FPGA Accelerator. (See “BittWare IA-840F FPGA Accelerator PCIe Card bristles with high-speed I/O, is based on an Intel® Agilex™ FPGA.”) The new IA-420F half-height, half-length, single-width PCIe card with multiple 100G network ports is designed for SmartNIC and computational storage applications and the IA-220-U2 computational storage processor in a U.2 form factor is specifically designed to accommodate NVMe computational storage workloads. BittWare provides all three FPGA-based accelerators with application reference designs and additional support for the Intel® oneAPI programming model, which provides hardware developers with the ability to create domain-specific FPGA platforms and allows application developers to build cross-architecture, single-source compilation designs.

 

 

BittWare has added the IA-420F half-height, half-length, single-width PCIe card and the IA-220-U2 computational storage processor in a U.2 form factor to its existing line of workload acceleration products based on Intel® Agilex™ FPGAs and FPGA SoCs.

 

According to BittWare, the IA-420F features a PCIe Gen4 x16 host interface that provides customers with as much as 2X the bandwidth normally available for FPGA-augmented systems, making it a compelling resource for accelerating data analytic workloads, while the IA-220-U2 can serve as a deployment-friendly computational storage processor in a U.2 NVMe storage array rack.

For more information about these accelerators, please contact BittWare directly.

 

For more information about the broad and growing line of Intel Agilex FPGA and SoC devices, click here, and be sure to read “Breakthrough FPGA News from Intel.”

 

 

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Published on Categories Acceleration, Agilex, StorageTags , ,
Steven Leibson

About Steven Leibson

Be sure to add the Intel Logic and Power Group to your LinkedIn groups. Steve Leibson is a Senior Content Manager at Intel. He started his career as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He’s served as Editor in Chief of EDN Magazine and Microprocessor Report and was the founding editor of Wind River’s Embedded Developers Journal. He has extensive design and marketing experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.