Be sure to read EEJournal’s new article about the world’s highest capacity FPGA, the Intel® Stratix® 10 GX 10M FPGA with 10.2 million LEs

Last month saw the announcement of the world’s highest capacity FPGA, the Intel® Stratix® 10 GX 10M FPGA with 10.2 million LEs (logic elements). (See “Intel announces Intel® Stratix® 10 GX 10M FPGA, world’s highest capacity with 10.2 million logic elements. Targets ASIC Prototyping and Emulation Markets.”) This device shipped to customers prior to the announcement and two leading vendors of ASIC prototyping tools, PRO DESIGN and S2C, have already announced ASIC prototyping systems based on the device. Both companies are members of the Intel Design Solutions Network.

This week, EEJournal.com’s editor-in-chief Kevin Morris weighed in on the Intel® Stratix® 10 GX 10M FPGA in an article titled “Intel’s ‘World’s Largest’ FPGA: The New Stratix 10 GX 10M.” If you’d like an objective analysis of this groundbreaking Intel® FPGA, Kevin Morris is certainly a good choice. He’s one of the industry’s leading FPGA authorities. Morris put more than a quarter of a century of engineering experience under his belt before founding Techfocus Media in 2003, which means he’s been analyzing and writing about FPGAs for more than an additional decade and a half, during the FPGA’s most dynamic period of capability growth.

I’m not going to rehash Morris’ entire article here, you need to read it yourself. But I do want to whet your curiosity, so here’s one of my favorite quotes from the article that demonstrates Morris’ perspective:

 

“In 2005, the largest FPGA consisted of fewer than 200,000 logic elements – not even the ‘.2’ part of today’s 10.2 million LUT unit. In the ‘10M’ part name, Intel rounded off more LUTs than the number in the entire ‘World’s Largest’ FPGA they previously bragged about.”

 

Take my advice, you want this guy’s perspective.

 

For more information about the recently announced ASIC prototyping systems based on the Intel® Stratix® 10 GX 10M FPGA, see:

 

 

 

 

 

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Steven Leibson

About Steven Leibson

Be sure to add the Intel Logic and Power Group to your LinkedIn groups. Steve Leibson is a Senior Content Manager at Intel. He started his career as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He’s served as Editor in Chief of EDN Magazine and Microprocessor Report and was the founding editor of Wind River’s Embedded Developers Journal. He has extensive design and marketing experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.