The US Defense Advanced Research Projects Agency (DARPA), has announced that researchers from Intel and Ayar Labs have demonstrated early progress towards improving chip connectivity using photonic interconnect under DARPA’s Photonics in the Package for Extreme Scalability (PIPES) program, which is exploring ways to expand the use of optical components to address the performance, efficiency, and distance constraints of copper interconnect. The demonstration successfully supplemented an Intel® FPGA’s electrical I/O with optical signaling by substituting a TeraPHY optical I/O chiplet developed by Ayar Labs for the SerDes chiplet – which Intel calls a “tile” – used in the original version of the Intel FPGA. The team integrated the Ayar Labs’ TeraPHY chiplet with the Intel FPGA core die into a multi-chip module (MCM) with in-package optics.
This image shows the optically connected FPGA board developed by Intel and Ayar Labs. Source: Ayar Labs
The packaged device communicates over an 8-channel optical link at 2 Tbps through its integrated, in-package optics. According to a blog titled “Breaking Optical I/O milestones while adjusting to the ‘new normal’” just published by Mark Wade, President and CTO of Ayar Labs, the demo “achieved a few key milestones” including a “512 Gbps transmitter with all 8 optical channels simultaneously locked and transmitting.” However, 2 Tbps is not the ultimate goal of the project. Dr. Gordon Keeler, the DARPA program manager leading PIPES, stated:
“A key goal of the [PIPES] program is to develop advanced ICs with photonic interfaces capable of driving >100 terabits per second (Tbps) I/O per package at energies below one picojoule per bit.”
The co-packaged TeraPHY chiplet communicates with the Intel FPGA die over an Advanced Interface Bus (AIB), which is a publicly available, open interface standard that enables silicon IP providers working under the PIPES program to create interoperable chiplets. (For more information about the AIB, see: Intel releases Royalty-Free, High-Performance AIB Interconnect Standard to Spur Industry’s Chiplet Adoption and Grow the Ecosystem, How Heterogeneous Device Design and Manufacturing Leads to Success, and Enabling Next-Generation Platforms Using Intel’s 3D System-in-Package Technology.)
The integrated optical MCM developed by this research team substantially improves interconnect reach, efficiency, and latency using optical I/O and enables high-speed data links over single-mode optical fibers connected directly to the MCM package. The Intel FPGA die used in this project was manufactured with an advanced Intel process technology and uses the same, established AIB interconnect employed by Intel® Stratix 10 and Intel® Agilex FPGAs to allow the FPGA die to communicate with a wide variety of co-packaged I/O tiles.
Intel’s silicon and software portfolio empowers our customers’ intelligent services from the cloud to the edge.
Note: For a detailed technical discussion of the TeraPHY chiplet, see this paper presented by Ayar Labs and Intel at the Hot Chips 2019 conference.
Notices and Disclaimers
Intel’s compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.
Software and workloads used in performance tests may have been optimized for performance only on Intel microprocessors.
Performance tests, such as SYSmark and MobileMark, are measured using specific computer systems, components, software, operations and functions. Any change to any of those factors may cause the results to vary. You should consult other information and performance tests to assist you in fully evaluating your contemplated purchases, including the performance of that product when combined with other products. For more complete information visit www.intel.com/benchmarks.
Performance results are based on testing as of dates shown in configurations and may not reflect all publicly available updates. See backup for configuration details. No product or component can be absolutely secure.
Intel does not control or audit third-party data. You should consult other sources to evaluate accuracy.
Your costs and results may vary.
Intel technologies may require enabled hardware, software or service activation.
Statements in this document that refer to future plans or expectations are forward-looking statements. These statements are based on current expectations and involve many risks and uncertainties that could cause actual results to differ materially from those expressed or implied in such statements. For more information on the factors that could cause actual results to differ materially, see our most recent earnings release and SEC filings at www.intc.com.
© Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others.
This image shows the optically connected FPGA board developed by Intel and Ayar Labs. Source: Ayar Labs
The packaged device communicates over an 8-channel optical link at 2 Tbps through its integrated, in-package optics. According to a blog titled “Breaking Optical I/O milestones while adjusting to the ‘new normal’” just published by Mark Wade, President and CTO of Ayar Labs, the demo “achieved a few key milestones” including a “512 Gbps transmitter with all 8 optical channels simultaneously locked and transmitting.” However, 2 Tbps is not the ultimate goal of the project. Dr. Gordon Keeler, the DARPA program manager leading PIPES, stated:
“A key goal of the [PIPES] program is to develop advanced ICs with photonic interfaces capable of driving >100 terabits per second (Tbps) I/O per package at energies below one picojoule per bit.”
The co-packaged TeraPHY chiplet communicates with the Intel FPGA die over an Advanced Interface Bus (AIB), which is a publicly available, open interface standard that enables silicon IP providers working under the PIPES program to create interoperable chiplets. (For more information about the AIB, see: Intel releases Royalty-Free, High-Performance AIB Interconnect Standard to Spur Industry’s Chiplet Adoption and Grow the Ecosystem, How Heterogeneous Device Design and Manufacturing Leads to Success, and Enabling Next-Generation Platforms Using Intel’s 3D System-in-Package Technology.)
The integrated optical MCM developed by this research team substantially improves interconnect reach, efficiency, and latency using optical I/O and enables high-speed data links over single-mode optical fibers connected directly to the MCM package. The Intel FPGA die used in this project was manufactured with an advanced Intel process technology and uses the same, established AIB interconnect employed by Intel® Stratix 10 and Intel® Agilex FPGAs to allow the FPGA die to communicate with a wide variety of co-packaged I/O tiles.
Intel’s silicon and software portfolio empowers our customers’ intelligent services from the cloud to the edge.
Note: For a detailed technical discussion of the TeraPHY chiplet, see this paper presented by Ayar Labs and Intel at the Hot Chips 2019 conference.
Notices and Disclaimers
Intel’s compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.
Software and workloads used in performance tests may have been optimized for performance only on Intel microprocessors.
Performance tests, such as SYSmark and MobileMark, are measured using specific computer systems, components, software, operations and functions. Any change to any of those factors may cause the results to vary. You should consult other information and performance tests to assist you in fully evaluating your contemplated purchases, including the performance of that product when combined with other products. For more complete information visit www.intel.com/benchmarks.
Performance results are based on testing as of dates shown in configurations and may not reflect all publicly available updates. See backup for configuration details. No product or component can be absolutely secure.
Intel does not control or audit third-party data. You should consult other sources to evaluate accuracy.
Your costs and results may vary.
Intel technologies may require enabled hardware, software or service activation.
Statements in this document that refer to future plans or expectations are forward-looking statements. These statements are based on current expectations and involve many risks and uncertainties that could cause actual results to differ materially from those expressed or implied in such statements. For more information on the factors that could cause actual results to differ materially, see our most recent earnings release and SEC filings at www.intc.com.
© Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others.