The Signal Tap Logic Analyzer, available in the Intel® Quartus® Prime software, captures and displays the real-time signal behavior designs instantiated in Intel® FPGAs. You can use the Signal Tap Logic Analyzer to probe and debug the behavior of internal signals during normal device operation without dedicating I/O pins to the analyzer and with no need for external lab equipment. The Signal Tap logic analyzer captures data continuously from specified signals based on specified trigger conditions that start and stop data capture. After capture, the data is available to transfer and display for analysis and debug. The Signal Tap Logic Analyzer is a powerful and flexible tool that novices and experts can use to get their designs to production faster.
During the upcoming “Office Hours” event (Thursday, January 28th, 8:00 to 9:00 am PST, 17:00 to 18:00 Central European Standard Time) you ask questions and discuss FPGA design debugging techniques with other designers. This is not a one-way Webcast. It’s an interactive discussion with an Intel Signal Tap Logic Analyzer expert and your engineering peers. No matter what level of experience you have, everyone is welcome to come and ask questions.
This “Office Hours” session will be run by Steven Strell, who has been in the Intel FPGA Training group for 13 years. His specialty areas include the hardware design tools found in the Intel Quartus Prime software, such as Platform Designer, and debugging tools like the Signal Tap embedded logic analyzer. Come and ask Steve your burning questions about FPGA-based design troubleshooting and debugging using the Signal Tap analyzer for Intel FPGAs.
To sign up for this session of Office Hours, go to Register for Debugging with Signal Tap for Intel FPGAs Office Hours.
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