Arrow Electronics™ develops four complete RF reference platforms based on the Intel® Arria® 10 SoC FPGA and Analog Devices high-speed RF transceivers, ADCs, and DACs

The JESD204B serial interface has become the interface standard of choice for high-speed analog-to-digital and digital-to-analog converters (ADCs and DACs). Intel® FPGAs and Intel® SOC FPGAs are well suited to interface to these converters using this interface and Arrow Electronics™ has developed four JESD204B reference solutions using high-speed analog RF transceivers and converter modules based on Analog Devices RF transceivers, ADCs, and DACs. These solutions employ third party carrier board platforms from Critical Link and iWave supporting production-ready Systems on Modules (SOMs) based on Intel® Arria® 10 SOC FPGAs.

The hardware for each of these platforms includes:

  • An Intel Arria 10 SoC FPGA SOM
  • A carrier card with an FMC HPC connector
  • An Analog Devices FMC converter board

 

Example reference designs for the platforms include:

  • JESD204B HDL code for the Intel Arria 10 SoC FPGA
  • Bootable Linux operating system image
  • Custom IIO Linux device drivers
  • Support for IIO Oscilloscope, an Analog Devices developed Linux user space application

 

Each reference platform also includes a unique Quick Start Guide and complete source code for an example design. All documentation is now freely available on GitHub.

The four Arrow Electronics reference platforms are:

The ADRV9371 Platform: The ADRV9371 Platform is a complete development platform for applications that require high-performance radios capable of operating over a wideband frequency range. This platform is based on the Analog Devices AD9371 dual RF transceiver, which has a tunable range of 300 MHz to 6000 MHz. The ADRV9371 FMC converter evaluation board connects to the Intel Arria 10 SoC FPGA using the JESD204B serial interface over an FMC connector at lane rates as high as 6.144 Gbps.

The ADRV9375 Platform: Similar to the ADRV9371 Platform, the ADRV9375 Platform connects an Intel Arria 10 SoC FPGA to an ADRV9375 evaluation board through an FMC connector using a JESD204B serial interface operating at lane rates as high as 6.144 Gbps. The Analog Devices ADRV9375 evaluation board is based on the Analog Devices AD9375 dual RF transceiver, which is similar to the Analog Devices AD9371 dual RF transceiver, but the AD9375 dual RF transceiver adds an on-chip digital pre-distortion (DPD) algorithm block.

The AD-FMCDAQ2 Platform: This platform connects an Intel Arria® 10 SoC FPGA to an AD-FMCDAQ2 evaluation board over an FMC connector using the JESD204B serial interface operating at lane rates as high as 6.144 Gbps. The AD-FMCDAQ2 evaluation board incorporates an Analog Devices AD9144 high-speed DAC and an Analog Devices AD9680 high-speed ADC.

The ADRV9371, ADRV9375, and AD-FMCDAQ2 reference platforms are ideal for developing a wide range of RF applications including:

  • 3G/4G micro and macro base stations
  • 3G/4G multicarrier picocells
  • FDD and TDD antenna systems
  • Microwave NLOS backhaul systems
  • Test and measurement applications
  • Software defined radios (SDR)

 

The ADRV9009 Platform: This platform connects an Intel Arria® 10 SoC FPGA to an Analog Devices ADRV9009 evaluation board over an FMC connector using the JESD204B serial interface operating at lane rates as high as 12.288 Gbps. The Analog Devices’ ADRV9009 is a wide bandwidth, high performance RF integrated transceiver with dual transmitters; dual receivers; and a dual-input, shared-observation receiver. This platform is ideal for developing a wide range of RF applications including:

  • 3G/4G/5G TDD Macro Cell Base Stations
  • TDD Active Antenna Systems
  • Massive MIMO
  • Phased Array Radar
  • Electronic Warfare
  • Military Communications
  • Portable Test Equipment

Loaner kits are available from Arrow Electronics for customers to evaluate these solutions.  Please contact your local Arrow rep for more information.

 

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Steven Leibson

About Steven Leibson

Be sure to add the Intel Logic and Power Group to your LinkedIn groups. Steve Leibson is a Senior Content Manager at Intel. He started his career as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He’s served as Editor in Chief of EDN Magazine and Microprocessor Report and was the founding editor of Wind River’s Embedded Developers Journal. He has extensive design and marketing experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.