APS Networks launches three OpenBNG Broadband Network Gateways incorporating Intel® Xeon® D processors, Intel® Tofino™ Switch ASICs, and Intel® Stratix® 10 MX FPGAs

Open BNG is an initiative within the Open Optical & Packet Transport (OOPT) Project Group’s Disaggregated Open Routers (DOR) sub-group, which is all part of the global Telecom Infra Project (TIP) that’s working to accelerate the development and deployment of open, disaggregated, and standards-based connectivity technology. TIP announced the initial release of the OpenBNG Technical Requirements document for large scale fiber-to-the-home (FTTH) networks – developed collaboratively by Telefónica, Deutsche Telekom, BT, and Vodafone – last October. The document encompasses:

  • Hardware and software requirements for an open and disaggregated Broadband Network Gateway (BNG) device that operators can deploy in current and future networks for the provision of fixed broadband services (OpenBNG)
  • The role of software-defined networks (SDN) and the desired approach for fixed-mobile convergence
  • The required hardware and proposed non-mutually exclusive software packages needed to support additional services or functionalities
  • Reference regulatory requirements to deploy Open BNG in the networks of the operators participating in the development of this requirements document

 

The OpenBNG specification allows operators a choice of different hardware platforms and types of network operating system (NOS) and control-plane applications, with goals of lowering the total cost of ownership and lowering the cost per broadband subscriber.

APS Networks has just launched three BNG switches which aim to comply with TIP OpenBNG requirements. Operators can choose among the SC-1, SC-2, and SC-3 TIP standard configurations for leaf designs that best address their end-user demands and cover both full-functionality deployments and service-only BNG deployments.

The APS Networks® announcement includes three BNG products:

  • The Hyperion APS2172Q, supporting 64×1/10/25G BNG user ports & 8x100G spine ports (SC-1)
  • The Jupiter APS6120Q with 16x100G BNG ports & 4×1/10/25G ports (SC-2)
  • The Hyperion APS2140D with 32×1/10/25G BNG user ports & 8x100G spine ports (SC-3 leaf)

 

The APS2172Q and APS6120Q each support as many as 32,000 broadband subscribers and the APS2140D supports as many as 20,000 broadband subscribers.

The announced BNG switches incorporate Intel® Xeon® D processors, P4-programmable Intel® Tofino™ Ethernet switch ASICs, and Intel® Stratix® 10 MX FPGAs with High-Bandwidth Memory (HBM). All BNG switch models can be equipped with a Precision Time Protocol (PTP) IEEE 1588v2 compliant add-on module, which enables the switches to operate as PTP boundary clocks with end-to-end accuracies of better than 10nsec.

Andy Heal, Chief Technology Officer for APS Networks, said “The APS Networks range of OpenBNG switches accelerate the possibilities for access edge solutions. Combining these low latency products of Intel Tofino P4-programmable switch ASICs and Intel Stratix 10 MX FPGAs, with world-class PTP capabilities and Intel Xeon D processors, APS Networks have designed and developed a unique range of network switches for the wireline broadband market.”

For more information about these APS Networks OpenBNG switches, please contact APS Networks directly. Click here.

 

  • For more information about Intel Xeon D processors, click here.
  • For more information about the Intel Tofino Ethernet Switch ASIC, click here.
  • For more information about Intel Stratix 10 FPGAs including the Intel Stratix 10 MX FPGAs, click here.

 

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Published on Categories Communications, Networking, StratixTags , ,
Steven Leibson

About Steven Leibson

Be sure to add the Intel Logic and Power Group to your LinkedIn groups. Steve Leibson is a Senior Content Manager at Intel. He started his career as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He’s served as Editor in Chief of EDN Magazine and Microprocessor Report and was the founding editor of Wind River’s Embedded Developers Journal. He has extensive design and marketing experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.