Free Webinar: Offload Hyperscale DDoS Attacks to SmartNICs and see a 300X performance improvement. July 30 - Distributed Denial of Service (DDoS) attacks are increasing in size, complexity, and severity. Service providers demand virtual security solutions that offer flexible and robust defenses against these increasingly frequent attacks. The F5 Networks BIG-IP VE for SmartNICs solution instantiated on an Intel® FPGA Programmable Acceleration Card N3000 can handle large DDoS attacks – as much...
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Free Functional-Safety Webinar: Discover How FPGAs Can Accelerate Your Safety Critical Application Development - Arrow and Intel are presenting a free Webinar that will introduce you to functional-safety design concepts and the reasons you will want put FPGAs at the heart of IEC 61508 compliant safe systems. The Webinar will also provide an in-depth look at the components of Intel's FPGA Functional Safety Data Pack and how the package...
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EEJournal and The Linley Newsletter cover the newly announced, AI-optimized Intel® Stratix® 10 NX FPGA - Last month, Intel announced the company’s first AI-optimized FPGA, the Intel® Stratix® 10 NX FPGA. (See “Intel has just announced its first AI-optimized FPGA – the Intel® Stratix® 10 NX FPGA – to address the rapid increase in AI model complexity.”) Earlier this week, The Linley Newsletter and EEJournal provided their perspectives on this announcement...
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THE LATEST
New Video: Intel® FPGA Partner Program members rENIAC and Megh Computing discuss expectations for Intel® oneAPI toolkits, heterogeneous computing workloads - Intel® oneAPI products will deliver the tools needed to deploy applications and solutions across a mix of scalar, vector, matrix, and spatial (SVMS) architectures – respectively CPUs, GPUs, specialized accelerators, and FPGAs. The Intel oneAPI set of toolkits—a base kit and specialty add-ons—simplify heterogeneous programming and help developers improve efficiency and innovation. A short, new...
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Why the Intel® FPGA Partner Program matters to partners and to their customers - Contributed by Lakecia Gunter, Vice President, Ecosystem Development and Operations, Intel Corporation Companies no longer compete one-on-one. Today, it's ecosystem versus ecosystem. The broadest ecosystem in which partners come together to develop and build solutions that deliver groundbreaking capabilities and solve key operational, technological, or business pain points will deliver the solutions that customers...
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VMware vSphere 6.7 now supports the Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA - According to this VMware blog published in January, VMware has expanded its array of supported hardware accelerators in its vSphere hypervisor to include support for the Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA (Intel® PAC with Intel® Arria® 10 GX FPGA). Why? The VMware blog explains: “The highly parallel architecture of FPGAs...
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New Video Demonstrates 116 Gbps PAM4 Transceiver Test Chip for Intel® Agilex™ I-Series FPGAs - A new Intel video shows the latest performance results for a high-speed, long-reach (LR) transceiver test chip operating at 116 Gbps with PAM4 modulation. The transceiver test chip, which is built with Intel 10 nm process technology, complies with the highest data rates of the CEI-112G-LR-PAM4 specification. The test chip’s 116 Gbps operation demonstrates the...
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Prevent DDoS attacks with the F5 BIG-IP Advanced Firewall Manager Smart Virtual Edition (AFMVE) integrated with an Intel® FPGA Programmable Acceleration Card (PAC) N3000 - The transition to 5G infrastructure will likely increase the risk of a new series of Distributed Denial-of-Service (DDoS) attacks. While DDoS attacks range from targeted acts of retaliation, protest, theft, or extortion to pranksters, they all have one objective: disrupt service availability and reduce the ability of a business to function. Service providers building 5G...
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Open vSwitch for NFVi based on Intel® FPGA Programmable Acceleration Card (Intel FPGA PAC) N3000 achieves first-packet learning rate of 500K rules/sec, near-wireline performance - As the numbers of subscribers, competitors, and technology advances grow, communications service providers (CoSPs) need to differentiate their products and services while keeping improved power efficiency and the need to control total cost of ownership (TCO) as ever-present goals. Intel and HCL have addressed these challenges with a joint solution that combines Intel® hardware and...
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Hardware Acceleration and Segment Routing over IPv6 (SRv6) help CoSPs Optimize and Simplify their Networks - Communications service providers (CoSPs) are seeking ways to differentiate themselves and to enhance their customers’ experiences in the fast-evolving telecommunication (telco) market—all while keeping costs under control. Exponential traffic growth and constant pressure to add more services and subscribers can tax legacy infrastructure, forcing CoSPs to constantly optimize and simplify their networks. Many CoSPs have...
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Can the new Intel® eASIC™ devices help you reach your 4G and 5G equipment design goals? - By Ronnie Vasishsta, VP and GM, Intel Corporation There is a lot of discussion in the industry today surrounding 5G telecommunications and networking. I even see television commercials about 5G popping up more and more. What's lost in all the excitement about 5G is that the 4G and 4G Advanced Pro standards are still...
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What’s Needed to Fully Realize the Promise of Heterogeneous Computing in Datacenters? - By Hua Xue, Vice President and General Manager, PSG Software Engineering, Intel Corporation The following guest blog is based on remarks by Hua Xue during a panel discussion on “FPGA Software Innovations” at the recent The Next FPGA Platform event, held last month in San Jose, California. Heterogeneous platforms are coming to the...
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How Heterogeneous Device Design and Manufacturing Leads to Success - By Patrick Dorsey, Vice President Product Marketing, FPGA and Power Products, Intel The following guest blog is based on remarks by Patrick Dorsey during a panel discussion on “FPGA Hardware Innovations” at the recent The Next FPGA Platform event, held in San Jose, California on January 22, 2020. One of the looming challenges...
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