Reinventing Storage for Social Networks with Intel® Xeon® Gold CPUs, Intel® Optane™ persistent memory, Intel® SSDs, and the Intel® PAC with Intel® Arria® 10 GX FPGA - Social networking is hugely data intensive. Consequently, data storage consumes a significant part of the budget for VK, Russia’s largest social network. In 2019, VK had 97 million monthly active users.1 Every day, users view 9 billion posts and 650 million videos, and they exchange 10 billion messages.2 They tap the “like” button a billion...
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Analog Devices and Intel collaborate on O-RAN compliant 5G development platform, melding ADI’s RF and Intel® FPGA technologies - Today, Analog Devices, Inc. (ADI) announced that it is collaborating with Intel to create a flexible 5G radio platform. This new O-RAN compliant platform combines the advanced technologies of ADI’s RF transceivers with advanced digital front end (DFE) functionality and Intel® Arria® 10 FPGAs to create a new set of design tools that address 5G...
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Financial Times article discusses Sulubaaï Environmental Foundation’s efforts to save coral reefs using smart underwater cameras and AI - Last week, the Financial Times published an article by Adam Green titled “Tech knowhow gives new lease of life to marine habitats.” The article discusses various efforts underway to combat the demise of sensitive marine ecosystems, especially coral reefs, and the first project discussed is the Sulubaaï Environmental Foundation’s efforts to regrow and rebuild Pangatalan...
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THE LATEST
IEEE 802.1 TSN IP and software from TTTech Industrial now available packaged with selected Cyclone® V SoC FPGAs - Time Sensitive Networking (TSN) is the IEEE 802.1 standard for deterministic packet transmission and handling over Ethernet networks. It is a set of evolving IEEE standards that support a mix of deterministic, real-time and best-effort traffic over fast Ethernet connections; provides precise time synchronization of network nodes using synchronized, distributed local clocks; and serves as...
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Learn how to use Intel® FPGAs in critical Functional Safety applications: two free on-demand training Webinars - Designs with formal functional safety requirements in markets such as industrial automation, transportation, the smart grid, automotive, military, aerospace, and medical require highly reliable systems that are certified to comply with established safety standards such as IEC 61508 and ISO 13849. Design challenges for such systems include: Adopting quality management standards and implementing a “safe”...
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Interested in using Intel® oneAPI Toolkit with FPGAs to accelerate your code? Free 6-hour Webinar. Register now - Intel® oneAPI Beta Toolkits will deliver uncompromised software performance for diverse workloads across multiple architectures, including Intel® CPUs and Intel® FPGAs, using Data Parallel C++ (DPC++). You can learn how to use these powerful new software-development tools in a free, 6-hour Webinar being held on May 19. This course will teach you how to use...
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Ciena leverages Intel technology for flexibility and programmability to accelerate the adoption of O-RAN in 5G New Radio (NR) and Next-Generation LTE. - Ciena recently announced three new xHaul (fronthaul, midhaul, and backhaul) routers – the multivendor interoperable Ciena 5164, 5166, and 5168 Routers – as described in a new Ciena blog written by Brian Lavallée, Senior Director of Portfolio Marketing at Ciena. Mobile networks use the xHaul transport networks discussed in Lavallée’s blog to interconnect cell sites...
read more- Accenture, the Sulubaaï Environmental Foundation, and Intel partner to create the CORaiL underwater vision system to help restore fragile coral reef ecosystems - Accenture has partnered with the Sulubaaï Environmental Foundation and Intel to develop an innovative solution for recreating and restoring coral reefs to their former health by installing special equipment including underwater cameras in the Pangatalan Island marine protected area in the Philippines. This system supports the Sulubaaï Environmental Foundation’s efforts to regrow and rebuild the...
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New Mantaro Networks System on Module (SoM) features Intel® Agilex™ FPGA and Intel® Enpirion® power devices - Mantaro Networks has announced the Model HTK-HPCSOM-AGF System on Module (SoM) based on a 10 nm Intel® Agilex™ AGF 014 FPGA. The SoM targets developers of high-performance computing (HPC), high-speed Ethernet networking at data rates ranging from 10 to 400 Gbps, signal and image processing, and 5G wireless applications. Mantaro Networks is located in Germantown,...
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Supermicro’s new short-depth 2U Ultra SuperServer for 5G and NFV applications incorporates two 2nd Gen Intel® Xeon® Scalable processors and supports the Intel® FPGA PAC N3000 accelerator card - Earlier this month, Supermicro announced a new, short-depth 2U Ultra SuperServer optimized to bring powerful industry-standard platforms to 5G and telecommunications environments. The new 2029U-MTNRV Ultra SuperServer supports two 2nd Gen Intel® Xeon® Scalable processors and the Intel® FPGA Programmable Acceleration Card N3000 (Intel FPGA PAC N3000), which can be used to accelerate 5G and...
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Intel introduces multi-phase, step-down power controller and power stage devices for high-current loads including core rails from 40 A to more than 200 A - Intel has introduced a solution for on-board power rails, including core rails, that incorporates pair of new Intel® Enpirion® power devices. These two new devices make it easy for you to design high-current step-down power converters for power trees with output currents spanning a wide load range from 40 A to more than 200 A,...
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Intel® Quartus® Prime Pro Edition design software suite version 20.1 with support for Intel® Agilex™ FPGAs is ready for download - The latest Intel® Quartus Prime Pro Edition software suite, version 20.1, is now available for download and you’re going to want it for the latest updates, which include the following additions and enhancements to make your design job much easier: The v20.1 release of the Intel® Quartus® Prime Pro Edition Software provides support for...
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Ayar Labs and Intel demo FPGA with optical transceivers in DARPA PIPES project: 2 Tbps now, >100 Tbps is the goal - The US Defense Advanced Research Projects Agency (DARPA), has announced that researchers from Intel and Ayar Labs have demonstrated early progress towards improving chip connectivity using photonic interconnect under DARPA’s Photonics in the Package for Extreme Scalability (PIPES) program, which is exploring ways to expand the use of optical components to address the performance, efficiency,...
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