What’s Needed to Fully Realize the Promise of Heterogeneous Computing in Datacenters? - By Hua Xue, Vice President and General Manager, PSG Software Engineering, Intel Corporation The following guest blog is based on remarks by Hua Xue during a panel discussion on “FPGA Software Innovations” at the recent The Next FPGA Platform event, held last month in San Jose, California. Heterogeneous platforms are coming to the...
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How Heterogeneous Device Design and Manufacturing Leads to Success - By Patrick Dorsey, Vice President Product Marketing, FPGA and Power Products, Intel The following guest blog is based on remarks by Patrick Dorsey during a panel discussion on “FPGA Hardware Innovations” at the recent The Next FPGA Platform event, held in San Jose, California on January 22, 2020. One of the looming challenges...
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The Three Levels of Heterogeneity: Devices, Systems, and Software - By Jose Alvarez, Senior Director, Intel CTO Office, PSG The following blog is adapted from a keynote speech that Jose Alvarez presented as the recent The Next FPGA Platform event, held in San Jose, California. There are three levels of heterogeneous integration. It’s a simple taxonomy. First, there’s heterogeneous integration at the chip...
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THE LATEST
Intel’s Kent Moffat explains the oneAPI initiative and beta release of Intel® oneAPI tools in a 3-minute video with insideHPC’s Rich Brueckner - Last month at the Supercomputing ’19 conference held in Denver, Intel rolled out the oneAPI initiative and a beta release of a comprehensive set of Intel® oneAPI programming toolkits. Inside HPC, the definitive blog about all things HPC, just published an article titled “Intel’s Kent Moffat describes the exciting new launch of oneAPI” with a...
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S2C’s free, 2-hour ASIC prototyping Webinar on December 10 will show you how to prototype billion-gate designs on world’s highest capacity FPGA - Last month saw the introduction of the Intel® Stratix® 10 GX 10M FPGA, the world’s highest capacity FPGA. This device specifically targets ASIC emulation and prototyping applications. Within days, S2C, a Gold member of the Intel® FPGA Design Solutions Network, announced that it was shipping a modular ASIC prototyping system based on this FPGA, the...
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Free Webinar on real-time, low-latency video analytics at the network edge or in the cloud using AI running on Intel® FPGA-based Programmable Accelerator Cards - If you need fast, real-time, low-latency video analytics for your application, then be sure to attend this free webinar to see how Megh Computing and Intel partnered together to extract actionable insights from streaming video data in real time, whether at the network edge or in the cloud, using AI and Intel® FPGA-based Programmable Accelerator...
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Free Intel® Agilex™ FPGA Webinar specifically for audiences in China on December 19: Ready to learn more about the new, faster, lower-power, 10nm Intel® FPGAs? - Intel® Agilex™ FPGAs and SoCs provide 40% faster core performance or 40% lower power consumption compared to previous-generation, high-performance, Intel® FPGAs. These FPGAs are designed to help engineers provide processor acceleration, tailored network transformation in data centers, and real-time acceleration with low latency at the edges of the network. Intel will present a Webinar about...
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Nuvation’s Angry Moose offline game relies on a Cyclone® V SOC to launch a small stuffed moose at a wall of beer cans - Nuvation Engineering, a Gold member of the Intel® FPGA Design Solutions Network, was clearly thinking out of the box (or out of the six pack) when it developed an offline, Canadian-flavored, mechatronic riff on the Angry Birds mobile gaming app. The Nuvation game is called Angry Moose and it consists of a 3D-printed slingshot that...
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Multi-rail power sequencer based on Intel® Max® 10 FPGA handles power-supply sequencing needs of CPUs, FPGAs, ASICs, and more - Sequencing regulated power to large ICs such as CPUs, FPGAs, and ASICs is a critical job that’s become increasingly complex as the number of power rails increases. The wrong power-up sequence can prevent a system from initializing properly and the wrong power-down sequence can cause data loss. If you’re facing a design with complex power-sequencing...
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Try the Intel® oneAPI(Beta) software and toolkit for FPGA development on the Intel DevCloud, for free - Intel announced the open oneAPI initiative, the unified Intel® oneAPI programming model and methodology, the associated Data Parallel C++ (DPC++) programming language based on Khronos SYCL, and several related toolkits last month at the Supercomputing 2019 conference held in in Denver. (See “Intel announces open oneAPI initiative and development beta release with Data Parallel C++...
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Photo of Intel EMIB bridge chip – a foundational packaging technology for Intel® CPUs, FPGAs, and GPUs – appears in the wild - Intel developed EMIB (Embedded Multi-die Interconnect Bridge) technology, a foundational packaging technology used in the manufacture of all Intel® Stratix® 10 GX, SX, TX, and MX FPGAs and Intel® Agilex™ FPGAs, to enable heterogeneous integration of multiple semiconductor die in one package. This high-speed interconnect technology has proven essential to the rapid development and proliferation...
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Gen-Z Consortium demos 5x SQLite database acceleration at SC’19 with an Intel UPI link between an Intel® Xeon CPU and an Intel® FPGA - Last week at the Supercomputing 2019 (SC’19) conference held in Denver, the Gen-Z Consortium demonstrated a proof-of-concept (POC) SQLite database acceleration demo that showed a 5x performance improvement in the average database INSERT operation time, with a clear path to even better performance. The demo employed a Gen-Z DRAM Memory Module (ZMM) with an integrated...
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Low-latency key-value store resides in FPGA SRAM, delivers data in a deterministic 500 nsec - Professor John Lockwood sits behind the wheel, piloting his slick electric roadster around a landscape filled with renewable energy sources: wind turbines, solar arrays, and a hydroelectric dam. He’s actually sitting at a simulation console in the Algo-Logic booth at the Supercomputing 2019 (SC’19) conference in the Denver Convention Center, watching the simulated world go...
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