2nd Generation Intel® Hyperflex™ FPGA fabric in Intel® Agilex™ FPGAs boosts Fmax by as much as 40% and cuts power, also by as much as 40%

Along with the recent announcement of Intel® Agilex™ FPGAs, Intel also introduced the 2nd Generation Intel® Hyperflex™ FPGA fabric architecture. A new 27-minute video recently posted on the Intel FPGA channel on YouTube titled “Intel® Hyperflex™ Architecture Overview for Intel Agilex™ Devices” provides deeply detailed explanations of the many new features.

Here are some highlights:

  1. The 2nd Generation Intel Hyperflex FPGA fabric includes numerous hyper-registers that make it possible to boost fabric clock rates significantly through hyper-pipelining. Even with hyper-pipelining, most of these hyper-registers will be in bypass mode. Consequently, a new high-speed bypass path has been added to the 2nd Generation Intel Hyperflex FPGA fabric to ensure that Intel Agilex FPGAs deliver faster performance. You can expect as much as a 40% performance improvement in clock rates over the 1st Generation Intel Hyperflex architecture in the Intel® Stratix® 10 FPGA families. That’s a significant performance boost.
  2. At the same time, careful transistor sizing in the 2nd Generation Intel Hyperflex FPGA fabric along with a process shrink to 10nm results in as much as a 40% reduction in power consumption. (Of course, power consumption is always determined by a combination of how much of the fabric is active and by the clock rate(s) used to operate the fabric.)
  3. A new, ASIC-like, synthesizable clock tree optimizes clocking resources within the 2nd Generation Intel Hyperflex FPGA fabric, which both improves maximum clock rates and reduces power consumption in the clock trees while making the FPGA fabric clocking networks far more flexible.
  4. In many cases, the latest version of Intel® Quartus® Prime Pro Design Software, version 19.3, automatically uses these new fabric features. (See “Intel® Quartus® Prime Design Software version 19.3 Pro Edition update software with new features and additional device support now ready for download.”)


Here’s the video:





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Steven Leibson

About Steven Leibson

Be sure to add the Intel Logic and Power Group to your LinkedIn groups. Steve Leibson is a Senior Content Manager at Intel. He started his career as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He’s served as Editor in Chief of EDN Magazine and Microprocessor Report and was the founding editor of Wind River’s Embedded Developers Journal. He has extensive design and marketing experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.