1U TeraBox 1400B Server from BittWare Holds four FPGA acceleration cards, two Intel Xeon Scalable Processors

Bittware has introduced the 1U TeraBox 1400B FPGA Server, which provides massive FPGA acceleration capabilities through its four PCIe Gen3 x16 slots. These four slots can accommodate as many as four Bittware FPGA boards including the BittWare 520N FPGA board – which is based on an Intel® Stratix® 10 GX FPGA – or the BittWare 520N-MX FPGA board – which is based on the Intel Stratix 10 MX FPGA that integrates 16 Gbytes of HBM2 memory into the FPGA package. The BittWare TeraBox 1400B FPGA Server also incorporates two Intel Xeon® Scalable processors.

Multiple in-box cooling fans maintain the passively cooled FPGA BittWare 520N and 520N-MX FPGA boards at the proper operating temperature and a 2000 W power supply provides ample power for both the Intel Xeon processors and the FPGA boards. Because it packs everything in a compact 1U box, the BittWare TeraBox 1400B FPGA server enables significantly higher FPGA-acceleration rack density than other FPGA servers, which are typically based on 4U form factors.

 

The BittWare TeraBox 1400B FPGA Server holds as many as four of the company’s PCIe FPGA accelerator cards.

The TeraBox 1400B FPGA server arranges the four FPGA boards within the server cabinet to reveal the four QSFP-28 optical cages on each BittWare 520N FPGA board. You can use these external QSFP-28 ports to directly interconnect the FPGAs in multiple BittWare TeraBox 1400B FPGA servers or to other types of servers in a server rack using appropriate breakout cables. Programming tools include the Intel Quartus® Prime Software Suite and a board support package (BSP) for OpenCL.

 

Please contact BittWare directly for more information about the Terabox 1400B FPGA server, the 520N FPGA card, and the 520N-MX FPGA card.

 

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Published on Categories Acceleration, Cloud, StratixTags , ,
Steven Leibson

About Steven Leibson

Be sure to add the Intel Logic and Power Group to your LinkedIn groups. Steve Leibson is a Senior Content Manager at Intel. He started his career as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He’s served as Editor in Chief of EDN Magazine and Microprocessor Report and was the founding editor of Wind River’s Embedded Developers Journal. He has extensive design and marketing experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.