Instruction Set Enhancements
posted by Brady Thomas on April 11, 2007
Moore’s Law gives me twice the number of transistors every 2 years with each new process generation. My goal is to use those transistors to provide greater customer value, which can come in the form of new capabilities or higher performance. Examples of new capabilities can range from virtual address extensions (like the 64 bit extensions introduced a few years ago) or new features like virtualization.
Additional performance can be delivered in a variety of different ways. Microachitecture enhancements which provide more computation per clock cycle is one technique. Larger cache also increase performance. Both of these provide additional performance on old binaries.
New instructions with the associated hardware support also provide more performance, but require new software to be written to use those instruction. We have successfully introduced new instructions over the years and will continue to do so in the future.
The challenge is to find something that can be by a wide range of applications or for specific applications like media processing that is widely used.
Once you add a new instruction it is EXTREMELY difficult to take it away. You have keep supporting it forever! Therefore, one must be careful to select functions that will be relevant over an extended period. Fortunately, with increasing densities, the burden of having to keep supporting “ancient” features is small.
In recent time we have been able to deliver good performance improvement at a relatively modest increase in transistor count.
Stay tuned for more as I continue this from Beijing. My big challenge tomorrow is getting home from Cleveland to San Jose via Chicago which has snow related delays! Hopefully I will get home in time to pack my bags and pick up my passport for the flight to Beijing for IDF.
Comments (6) (closed)
tagged: extensions, instruction set, microarchitecture, Moore's Law, performance
Comments
Apr 24 | Dileep Bhandarkar said:
For details on how to use the 47 new SSE4 instructions in the 45nm Next Generation Intel® Core™ Microarchitecture Processor(Penryn) look at Mark Buxton’s IDF presentation
https://intel.wingateweb.com/published/BMAS005/BMAS005_100Eng.pdf
Apr 26 | Dileep Bhandarkar said:
This may be more interesting than my views :-)
http://www.dilbert.com/comics/dilbert/archive/dilbert-20070426.html
Apr 28 | John Bates said:
Question re: Moore’s Law. I’ve heard that after so long, the smaller and smaller the transistors that the electrons themselves start to behave erratically, jump, etc. What then? How will Moore’s Law respond? What can we expect to see? Thx.
Apr 29 | Dileep Bhandarkar said:
This is certainly an issue to be concerned about beyond 22 nm. There are several research activities in the academic and industrial community to find ways of mitigating this.
We did not see any show stoppers for the next few process generations at least up to 22 nm.
May 11 | Igor said:
Still no gather/scatter for SIMD and MOVNTDQA cannot be used for WB memory type. If you have 2x the transistors each time at your disposal then why do you teaspoon-feed us developers with features?
May 18 | Dileep Bhandarkar said:
I will no longer be contributing to this blog topic and will not be reviewing and approving comments.
Please consider this topic to be closed.