Intel Discusses Future Research Options at IEDM 2015

This year marks the 50th anniversary of Moore’s Law, which Intel continues to relentlessly pursue because it drives innovation up and costs down for us and the industry as a whole. While the process of scaling silicon is challenging, our research pipeline is full of options that can help us secure the future of Moore’s Law and enable new functions. At the IEEE International Electron Devices Meeting (IEDM), which takes place in Washington D.C. this week, Intel’s Components Research (CR) organization – the team responsible for process technology research — is presenting advances in three areas:

  1. Beyond-CMOS devices
  2. GaN (gallium nitride) devices
  3. Non-silicon CMOS devices

Beyond-CMOS Devices

As nanoelectronics approaches the nanometer scale, a worldwide, beyond-CMOS research effort is underway to identify the next scalable logic device technology beyond conventional charge-based transistors1. Such computing technology needs to a) provide significant improvements in switching energy and delay, b) address interconnect resistance and capacitance scaling and c) provide a complete logic plus memory family. Some examples of beyond-CMOS device options being investigated by Intel CR, universities and research consortia include the quantum tunneling based Tunneling FET device (T-FET), Spin Torque Majority Gate (STMG) device, spin torque logic device, Spin Wave Majority Gate (SWMG) device, and magneto-electric switching of spintronic logic device, as shown in the figures below.

Beyond-CMOS Device Options Intel is Investigating

At the IEDM, Intel is presenting two research papers on the Tunneling FET (T-FET) devices. Reducing supply voltage while keeping leakage current low is critical for minimizing energy consumption and improving battery life for mobile electronics. The thermal limit of MOSFET subthreshold swing restricts lowering the transistor threshold voltage, causing performance degradation at ultra-low voltage operation, for example, less than 0.5V. The T-FET is not limited by this thermal limit and may perform better at ultra-low voltages. Since the first experimental proof of subthreshold swing steeper than 60mV/decade, the T-FET’s prospects have attracted the interest of researchers since it may enable future ultra-low power circuits. In the first paper entitled “Tunneling Field Effect Transistors: Device and Circuit Considerations for Energy Efficient Logic Opportunities”, the device and circuit considerations of the T-FET to take advantage of its steep subthreshold swing will be discussed. Experimental realization of T-FETs with steep subthreshold swing requires overcoming various process challenges. In the second paper titled “Study of T-FET Non-ideality Effects for Determination of Geometry and Defect Density Requirements for Sub-60mV/decade Ge T-FET,” a comprehensive study of T-FET geometry and material quality is carried out with experimentally calibrated models, showing the path for realizing target T-FET transistors and the physics behind these challenges.

Also in the beyond-CMOS research space, Intel CR is co-authoring with research organizations IMEC and EPFL an IEDM paper entitled “Spintronic Majority Gates.” In this paper the spin torque majority gate (STMG) and spin wave majority gate (SWMG) devices are discussed and compared.

GaN (gallium nitride) Devices

GaN is a wide band-gap semiconductor material that has many unique and interesting electrical properties. Among GaN, GaAs and Si materials, GaN has the highest Baliga and Johnson Figure of Merits (FOM), as shown in the table below, making it advantageous for high voltage power electronics and high frequency electronics. In addition GaN demonstrates unique polarization properties that give rise to unique and interesting device characteristics2.

GaN Table Dec 09 2015Intel’s GaN paper at the IEDM is titled “High-K Gate Dielectric Depletion-Mode and Enhancement-Mode GaN MOS-HEMTs for Improved OFF-state Leakage and DIBL for Power Electronics and RF Applications.” In this paper CR will report on (i) a depletion-mode GaN device which exhibits “negative” gate capacitance and subthreshold swing steeper than 60mV/decade, which may have implications to future low-power electronics, and (ii) an enhancement-mode GaN device that exhibits excellent DIBL, low off-state leakage, low gate leakage, high breakdown voltage and also low on-resistance, which are attractive device properties for power electronics and RF applications.

Non-silicon CMOS Devices

For the non-silicon CMOS device research topic3, CR is presenting a computer modeling paper using atomistic quantum transport simulations to compare Si, Ge and III-V nanowire devices for future scaled transistor technologies and examine nanowire CMOS performance with various combinations of n- and p-type channel materials. The paper is entitled “CMOS Performance Benchmarking of Si, InAs, GaAs, and Ge Nanowire n- and pMOSFETs with LG=13 nm Based on Atomistic Quantum Transport Simulation Including Strain Effects.”

References:

[1] D. E. Nikonov and I. A. Young, “Overview of Beyond-CMOS Devices and a Uniform Methodology for Their Benchmarking,” Proc. IEEE, Vol. 101, pp. 2498 – 2533, 2013.

[2] H.W. Then, et al., “Experimental Observation and Physics of Negative Capacitance and Steeper than 40mV/decade Subthreshold Swing in Al0.83In0.17N/AlN/GaN MOS-HEMT on SiC Substrate,” IEDM December 2013.

[3] K. Kuhn, et al., “The Ultimate CMOS Device and Beyond,” IEDM December 2012.

Robert S. Chau is an Intel Senior Fellow and co-director of Components Research in the Technology and Manufacturing Group at Intel Corporation.

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