By Sanjay Natarajan, Vice President, Technology & Manufacturing Group and Director, Process Technology Integration
Lately, we often get asked: “Is process scaling coming to an end?” Since no one believes that process development will just end one fine day, a more nuanced version of this question is whether it is becoming technically impossible, or at least practically infeasible, to develop and deploy new processes roughly every two years as envisioned by Moore’s Law nearly 50 years ago.
Before we pull out our crystal ball to tackle this question, a little historical perspective is called for. The early days of process technologies were, in hindsight, a much simpler time. The basic architecture of the MOS transistor was static, and the path to developing a new process was clear and straightforward: scale the lateral dimensions, scale the vertical dimensions, scale the electric fields, and voila – a fabulous hat trick of smaller, lower-power, and faster transistors. Certainly inventions such as tip and halo implants, salicides, and nitrided gate oxides were required to solve problems along the way, but the basic architecture remained the same for many generations. (While we’re on the subject of inventions, let’s not forget about the interconnect stack, where copper interconnects and planarization were invented.)
The End of Scaling?
Even in this “heyday,” industry experts were predicting the end of scaling. Expert statements such as “Optical lithography will reach its limits in the range of 0.75-0.50 microns,” “Minimum geometries will saturate in the range of 0.3 to 0.5 microns,” “X-ray lithography will be needed below 1 micron,” “Copper interconnects will never work,” and “Scaling will end in about 10 years,” were made publicly, and all seem quaint in hindsight.
The 130nm technology node was perhaps the last true technology in this architecture. The early 1990s marked a seismic shift in our industry with Intel’s invention of uniaxial strained silicon in the 90nm generation. This change – marked by the use of epitaxially grown Silicon-Germanium in the PMOS source/drain – ushered in an era of major materials changes in addition to existing dimensional and electrical scaling. The 65nm node was the last node to utilize the workhorse of the industry, the SiON gate dielectric. Starting with 45nm, Intel made the switch to exotic Hafnium-based high-k dieletrics with complex sandwiches of interface films. Finally, the 22nm node heralded the end of the 50-year life of the planar MOS transistor with a move the 3D trigate transistors. Today’s state of the art resembles the late 1980s transistor about as much as a Ferrari resembles a horse-drawn carriage.
Not only have transistor structure and materials changed dramatically over the past decade, but the goal of transistor scaling has also changed. The 1980s and 1990s were an era where classical scaling provided significant improvements in transistor speed to enable microprocessor products with ever-higher operating frequencies. But we were paying the price of ever-higher power density and ever-higher leakage power in doing so. The 2000s ushered in an era where power-density limits and market demands for mobile computing changed the focus of transistor technology from increased performance to lower power. Today’s computing products, whether they are for high-performance servers or low-power cell phones, all place premiums on improved energy efficiency and lower leakage power. And the rise in interest in system-on-chip (SOC) products places increased importance on providing a wider range of devices on a single chip, from high-performance to ultra-low-leakage transistors.
Radical New Approaches Coming
This historical perspective is important, because it reminds us that the only constant in our industry is change (or, as Yogi Berra put it, “the future ain’t what it used to be”). In the future, radical new architectures may create another seismic shift when just improving on what we have ceases to work. Many potentially attractive options exist – tunnel FETs, BISFETs, Graphene-based FETs, and Spin-based FETs, just to name a few. All are being actively researched at leading semiconductor companies and consortia.
Another trend of growing importance is the tighter integration between process technology, product design, and product architecture. Over the past few generations, limitations in process scaling have led to design-rule constraints, which in turn have required greater co-optimization between design and process to maximize value. This trend is likely to continue and even grow in scope. The future will include novel process, design, and architecture integration such as 3D stacking (within a chip, not just TSV stacking) and new approaches to computation, such as process technology optimized for non-Boolean logic.
It’s entirely possible that the new process architectures of tomorrow will make today’s Ferrari look like a horse-drawn carriage. As we work to make that happen, this is a very exciting time for the semiconductor industry, and we look forward to another 50 years of Moore’s Law!