by Mike Mayberry, Vice President, Technology & Manufacturing Group, and Director, Components Research
Welcome! I’ve been blogging about research progress towards making compound semiconductors mainstream and talking about both challenges and opportunities. Three IEDM 2011 papers show the latest progress so in this installment I’ll talk about the papers and how they relate to our challenges.
First as a reminder, unlike silicon, a compound semiconductor is made up of two or more elements, indium, gallium and arsenic for example (InGaAs). The key advantage of these materials is high charge mobility. Mobility is a measure of how easily you can move charges within the material with application of an electric field. Higher mobility can produce faster devices and/or devices that require much less power. Using two or more elements means more opportunity to tune the materials for performance or optical properties but also makes the challenge of fabricating wafers and processing much more complicated. Today, compound semiconductors are used in smaller scale applications where their special properties outweigh the added costs. Our goal is to take advantage of the vastly larger spending on silicon infrastructure and put it to use fabricating compound semiconductor devices.
Let’s look at how a generic transistor behaves over a range of control voltages in figure 1. On the left I’ve plotted the current on a linear scale while on the right I’ve used a logarithmic scale. Since a modern transistor can have a current ratio in the range 10,000 to 100,000, you can see why it is tough to see both on the same scale. The plot on left is best to understand how the device turns on while the right shows what happens as the device turns off. In the real world, better on state performance leads to higher switching speeds and thus more potential computations per second. Better off state means the stand-by state doesn’t run down your battery.
Fig 1: Device behavior can be plotted on a linear scale to examine turn-on behavior or on a logarithmic scale to examine turn-off behavior.
A physically short device has lower internal resistance so typically turns on faster but also is harder to completely turn off, thus it can have a poorer on-off ratio. Device engineers use multiple figures of merit but for this blog I will only focus on subthreshold swing (SS). SS is defined as the amount of voltage required to swing the off current by a factor of 10x and it is the inverse of the subthreshold slope shown in figure 1. An ideal device at room temperature will have SS=60mV per decade. Extra leakage paths and low coupling will raise SS and a poor device might have SS>150 for short dimensions. It doesn’t seem like much but that difference can lead to orders of magnitude difference in leakage power.
We have been working to optimize our compound semiconductor devices to both reduce parasitic effects and to increase the coupling by creating a trigate structure. In the first IEDM 2011 paper we show that an optimized III-V trigate device can have a much better SS than the equivalent planar device at short dimensions. A trigate device out performs in SS even with a trigate fin width of 30nm versus the 10nm thin body planar device. We are not yet at a point to claim both better and smaller compared with the best silicon trigate but we’re now one step closer.
In my last blog I talked about how a tunnel FET (TFET) might perform better under lower operating voltages because it has a steeper current cutoff (fig 2). In other words SS is lower, though in the case of a TFET it is not a straight line on a log scale.
Fig 2: Two modeled InAs double gate TFET configurations show very different turn-off behavior compared to the scaled CMOS device.
Our second IEDM paper is experimental work on III-V tunnel FET (TFET) devices. We show that we can achieve lower SS over part of the voltage range compared to the same thin body planar and for some of the operating range achieve steeper than 60 for SS. Again we’re not yet able to claim better than silicon but one step closer.
Fig 3. Cross-section of a single gate III-V tunnel FET. Gate is formed down the left side of the structure.
Our final paper which is unrelated to the other two looks at potential manufacturing techniques. Forming these devices requires precise growth of multiple crystalline layers using different materials. Most of our work to date has used Molecular Beam Epitaxy (MBE) which excels at fine control but has a very slow rate of deposition. We are currently evaluating Metallorganic Vapor Phase Epitaxy (MOVPE) as an alternative and we report that we can achieve equivalent mobility. Given that it is both faster and potentially opens up choices for selective deposition, this work establishes viability of MOVPE for the future.
Wrapping up, integration and optimization is about controlling many small details. It takes very few impurities to create leakage paths and as we move to very small dimensions, optimizing the design of the structure and the engineering of the interfaces becomes critical. We have years of practice on silicon so even when a non-silicon material starts out with an inherent advantage, a lot of invention is required to catch up. Research is continuing in order to make compound semiconductors with superior power-performance compared to the best silicon can offer today.
- Electrostatics Improvement in 3-D Tri-gate Over Ultra-Thin Body Planar InGaAs Quantum Well Field Effect Transistors with High-K Gate Dielectric and Scaled Gate-to-Drain/Gate-to-Source Separation, M. Radosavljevic et al., IEDM 2011.
- Fabrication, Characterization, and Physics of III-V Heterojunction Tunneling Field Effect Transistors (H-TFET) for Steep Sub-Threshold Swing, G. Dewey et al., IEDM 2011.
- MOVPE III-V Material Growth on Silicon Substrates and its Comparison to MBE for Future High Performance and Low Power Logic Applications, N. Mukherjee et al. IEDM 2011.
A very good survey paper of III-V opportunities and challenges:
Nanometre-scale electronics with III-V compound semiconductors, Jes