Enforcing Moore’s Law through Technology Research – Part 4

Welcome to the fourth installment! I’ve been blogging about research progress towards making compound semiconductors mainstream and talking about both challenges and opportunities.

Enforcing Moore’s Law through Technology Research

Enforcing Moore’s Law through Technology Research – Part 2

Enforcing Moore’s Law through Technology Research – Part 3

In this blog, I’ll update the progress and give a look ahead to some of the upcoming research projects.

First as a reminder, unlike silicon, a compound semiconductor is made up of two or more elements, indium, gallium and arsenic for example (InGaAs). Using two or more elements means more opportunity to tune the materials for performance or optical properties but also makes the challenge of fabricating wafers and processing much more complicated.

Today, compound semiconductors are used in smaller scale applications where their special properties outweigh the added costs. Our goal is to take advantage of the vastly larger spending on silicon infrastructure and put it to use fabricating compound semiconductor devices. I gave five individual challenges which needed to be solved in order to allow broader use of compound semiconductor technology and we are working both internally as well as with external groups such as universities to make progress on this list.

1. Build compound semiconductor devices on silicon substrates. That would allow us to reuse the highly refined silicon infrastructure including 300mm wafers and down the road gives us the option of integrating a few specialized devices with a sea of silicon devices.

Today we are able to grow a wide variety of III-V quantum wells (the regions where electrical switching occurs) on top of silicon substrates. Our technique involves creating a graded buffer layer which gradually changes the lattice spacing, traps dislocations, and finally prepares a high quality barrier layer under the quantum well. You can see an example here from IEDM 2007: http://www.intel.com/technology/IEDM2007/III-V_paper.htm.

At this year’s upcoming IEDM 2010, we will report using similartechniques to grow a Ge channel quantum well device on top of silicon [Ref 1]. Our focus has been on both growing the tool box to allow wider choices for materials and on looking ahead to which methods will scale best for manufacturing.



Find a suitable high K gate dielectric. Due to the different surface,the silicon high K solution won’t work as is but we can leverage knowledge we gained to help guide us.

Here also the key is choice of materials and specific application techniques. Last year we reported high k dielectric results with InGaAs;this year we report on a different high k material system on Ge. Both results show a possible path forward and both also illustrate key sensitivities associated with transitions between different materials.

Reducing the equivalent trapped charge at the interfaces is the only way to achieve high performance devices and in both cases the key was the choice of a particular transition layer instead of putting the high k directly on the channel material.


Build a high performance PMOS device to go with the existing NMOS. This is needed to have power efficient CMOS logic though some special circuits can get by with just one type.

Here’s where the focus on germanium comes in. Germanium is not a III-V material but rather a group IV material like silicon. The first transistors were based on germanium but were replaced by silicon in large measure because silicon oxide is a very good gate dielectric.

Germanium though has superior mobility and if one could create a good gate dielectric then a much higher performance P channel device could be created. A key result in our paper is showing higher performance for a Ge QW than the strained InSb QW that we reported in 2008, narrowing the gap between the very high performance N channel III-V and a possible P channel device to complement it.

4. Build enhancement devices. Most existing work is based on depletion mode where you apply a voltage to shut them off. Power efficiency demands that those devices be normally off.

Here we have shown we can adjust the operation of the device by varying geometry and that we can suppress parallel conduction channels through the barrier layers. Those adjustments allow enhancement mode operation.

5. Make them small enough to compete with silicon transistor densities. If we stop at integrating only a few specialized devices then this is not needed but then we also won’t reap the full benefit of the technology.


A quantum well field effect device (QWFET) is created with a very thin (~10nm) high-mobility layer sandwiched between two high resistance barriers. Because the quantum well is undoped and its interfaces are smooth, scattering is suppressed, and charges can move very quickly.


Fig 1: Generic diagram of QWFET structure compared with MOS

Past research work has shown that the gate can be made very short

(left to right dimension in this figure) for both silicon and III-V’s

but at very short distances it becomes harder to turn the device off. To

cope with this problem, you need to move the gate closer to the channel

(high k dielectrics), thin the channel (fully depleted devices), or add

additional gates on the opposite side (finFETs and other multi-gate

devices). The second paper coming at IEDM 2010 covers work on building

and characterizing a non-planar, multi-gate III-V device [Ref 2].

Without pre-publishing the data, the device does indeed behave as

expected, having better short channel performance as measured by

subthreshold swing.

While expected, nevertheless this is an important result. A quantum

well device depends on confinement to create high mobility. When you

reduce the dimensions of the device in other directions, it is not clear

how the charge transport will change. We still have work to do to make

the devices still smaller to explore this behavior. Here is an example

of a fin where the channel width is smaller than the quantum well. We

don’t yet know how this will behave as a device.


Fig 2: A tall thin fin of Indium Gallium Arsenide.

Recapping the challenge list, we have made substantial progress on

all of the basic material integration challenges (items 1-4) and have

started to make progress on density (item 5). We are generally on track

to where we expected to be today.

While our list of challenges we made in 2006 was a useful starting

point we can now list many other areas which require further work before

we can predict the timing for roadmap intercept and this includes

determining where the circuit benefit is high enough to pay for the

complexity of integration. This option needs to be weighed against other

implementations and extensions of silicon to choose the best technology

at each generation.

Ref. 1: High Mobility Strained Germanium Quantum Well Field Effect

Transistor as the P-Channel Device Option for Low Power (Vcc=0.5V) III-V

CMOS Architecture, R. Pillarisetty, B. Chu-Kung, S. Corcoran, G. Dewey,

J. Kavalieros, H. Kennel, R. Kotlyar, V. Le, D. Lionberger, M. Metz, N.

Mukherjee, J. Nah, W. Rachmady, M. Radosavljevic, U. Shah, S. Taft, H.

Then, N. Zelick, and R. Chau.

Ref 2: Non-Planar, Multi-Gate InGaAs Quantum Well Field Effect

Transistors with High-K Gate Dielectric and Ultra-Scaled

Gate-to-Drain/Gate-to-Source Separation for Low Power Logic

Applications, M. Radosavljevic, G. Dewey, J.M. Fastenau, J. Kavalieros, R. Kotlyar, B. Chu-Kung, W. K. Liu,

D. Lubyshev, M. Metz, K. Millard, N. Mukherjee, L. Pan, R.

Pillarisetty, W. Rachmady, U. Shah, R. Chau, Intel Corporation, IQE,



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