IDF, skeptical students, 22nm and the relentless pursuit of Moore’s Law

IDF tends to generate excitement among interviewing graduate students (all the fascinating new technologies discussed at IDF ranging from in-vehicle infotainment, through common connected computing and cloud computing, and to such “green” concepts as smart grid, provides great motivation for interviewing at Intel!). However, a very common question I get asked during interviews around IDF time is “Is scaling coming to an end?

Well, Moore’s Law and transistor scaling are not showing any sign of slowing down! In November of 2009 Intel announced that it had started production shipments of microprocessors based on our newest 32nm generation of logic technology. More simply, the first 32nm products started shipping exactly 2 years after the first 45nm products (and before any others in our industry). If students get skeptical when I say this, I just love showing them our 8 generation yield graph – which shows the past 4 technologies lock-step at 2-years (or maybe even a bit LESS than two years). This incredible achievement from our engineering and manufacturing teams means that cost per transistor continues to drop every generation – enabling new technologies like those showcased at IDF.

However, these IDF-inspired students (concerned no doubt about having a job in 2 years!) tend to question me about what is coming in beyond 32nm. I love telling them that our advanced 22nm logic technology is fully in development and on track for production readiness in late 2011. (Of course, if I say this to a student, it sounds suspiciously like advertising – so the students retaliate by asking specific questions about data.) This is where things get fun. Traditionally, a new technology is demonstrated with a test vehicle product (often called a shuttle) that includes SRAM devices, collateral circuit block, and individual device test structures. It delights me to remind them that Intel has been the first to demonstrate working 22nm circuits on such a test vehicle.

Furthermore, while individual transistors and test circuits provide critical information for process development, the real benchmarks in these test vehicles are the SRAM arrays. The 22nm SRAM circuits Intel has demonstrated use the smallest SRAM cell (0.092 um2) in working circuits and largest SRAM array (364 Mbit) reported to date. Each of these SRAM chips has over 2.9 billion transistors!

 

I do remind students that Moore’s Law is changing. Traditional transistor scaling (where smaller dimensions alone provide improvement) has become less influential in Moore’s Law scaling. Therefore, in generations after the 130nm node (90nm, 65nm, 45nm, 32nm, 22nm etc.) performance enhancers have been added to continue to drive the transistor roadmap forward (e-SiGe and strained SiN for strain in the 90nm and 65nm nodes, and high-k metal-gate (HiK-MG) in the 45nm and 32nm nodes.

Moore’s Law and transistor scaling are not showing any sign of slowing down, but they are showing signs of changing to better meet today’s market requirements. Achieving very high operating frequencies is no longer the prime target for new microprocessors. Instead, the goal has shifted to delivering higher performance combined with lower power.“Power efficiency” is the main scaling goal for chips used both in small hand held devices and in large data centers. So, the goals have shifted a bit, and the technology options are changing over time, but the value and excitement of driving Moore’s Law remain undiminished.

 

5 Responses to IDF, skeptical students, 22nm and the relentless pursuit of Moore’s Law

  1. Saurabh says:

    Hi Kelin
    I am one of the students near graduation (in a year and a half probably :) ) and I have a similar doubts regarding Moore’s law and scaling. From what I’ve read and heard, scaling will most definitely continue up to 16nm node and I am sure that Intel will lead the initiative. I am curious about Intel’s plan after that, which I am sure, won’t be divulged now.
    How do you make conventional planar devices beyond 16nm? Do you plan to shift to ‘new’ materials such as carbon based transistors (CNT/graphene) or nanowires? However, none of these novel material based transistors have been implemented and demonstrated in a full-scale microprocessor with higher device density and functionality compared to Si based devices. Hence the question comes up again, will Moore’s law continue beyond 16nm…if yes, how?

  2. Kelin Kuhn says:

    Saurabh,
    I’m delighted by your interest in our long term scaling roadmap! Although I can’t provide details as to Intel’s (or anyone elses!) silicon roadmap and its timing – I can say that there are a large number of options for the future. For example, the short-channel effects of conventional planar devices can be improved by using ultra-thin body (UTB) transistors. The logical “next step” after UTB devices are multiple gate devices (MuGFETS) such as double-gate, trigate, FinFET, Pi-FET, Omega-FET devices and the like. After MuGFETs, the next step is some type of gate-all-around architecture (nanowires and related devices). All of these devices are much more mature than CNTs, and many of them have already been demonstrated in the literature in circuit applications such as SRAM devices. But the structural (electrostatic confinement) roadmap is only part of the picture – as research is also proceeding on materials innovations. Advanced strain techniques and wafer orientation are on the short term horizon and innovations such as Ge channels, and III-V materials are on the intermediate and long term horizon.
    In answer to your question about Moore’s Law beyond 15nm …. predicting Moore’s Law development at ANY point in time is somewhat like headlights in the fog – we always know how to do the next generation, we have some really good ideas about the subsequent generation and we can somewhat see the one after that. That is no different today than it was five generations ago :-) .
    k

  3. Jim says:

    Hi Kelin,
    I am interested in cutting edge process-design interaction. Intel adopted RDR layout on 45nm technology node. As Mr. Bohr indicated earlier RDR@45nm has nothing to do with gate-last but tries to work with 193 “dry” litho tool. For 32nm, Intel changes to “immersion” tool. Then does Intel follow RDR at 32nm?

  4. Kelin Kuhn says:

    Jim, It turns out that restricted-design-rules (RDR) have more value than just extending the lithography roadmap. They also provide benefits for many other modules (ex: polish and etch) and these benefits translate into improved density (i.e. lower cost) and higher yields. As a consequence, RDR introduced in one technology are carried forward into the next generation because of the continued value-add going forward.

  5. Mai Pham says:

    “Moore’s Law and transistor scaling are not showing any sign of slowing down, but they are showing signs of changing to better meet today’s market requirements.” I totally agree with this. You know, I’m the last grade student, major in computer engineering. I was born and grow up in Vietnam, where you can find the Intel Company (I’m pround to say that).
    I don’t know the next generation is. But I know it’ll be smaller and smaller.
    Thanks for your helpful post.