IDF tends to generate excitement among interviewing graduate students (all the fascinating new technologies discussed at IDF ranging from in-vehicle infotainment, through common connected computing and cloud computing, and to such “green” concepts as smart grid, provides great motivation for interviewing at Intel!). However, a very common question I get asked during interviews around IDF time is “Is scaling coming to an end?
Well, Moore’s Law and transistor scaling are not showing any sign of slowing down! In November of 2009 Intel announced that it had started production shipments of microprocessors based on our newest 32nm generation of logic technology. More simply, the first 32nm products started shipping exactly 2 years after the first 45nm products (and before any others in our industry). If students get skeptical when I say this, I just love showing them our 8 generation yield graph – which shows the past 4 technologies lock-step at 2-years (or maybe even a bit LESS than two years). This incredible achievement from our engineering and manufacturing teams means that cost per transistor continues to drop every generation – enabling new technologies like those showcased at IDF.
However, these IDF-inspired students (concerned no doubt about having a job in 2 years!) tend to question me about what is coming in beyond 32nm. I love telling them that our advanced 22nm logic technology is fully in development and on track for production readiness in late 2011. (Of course, if I say this to a student, it sounds suspiciously like advertising – so the students retaliate by asking specific questions about data.) This is where things get fun. Traditionally, a new technology is demonstrated with a test vehicle product (often called a shuttle) that includes SRAM devices, collateral circuit block, and individual device test structures. It delights me to remind them that Intel has been the first to demonstrate working 22nm circuits on such a test vehicle.
Furthermore, while individual transistors and test circuits provide critical information for process development, the real benchmarks in these test vehicles are the SRAM arrays. The 22nm SRAM circuits Intel has demonstrated use the smallest SRAM cell (0.092 um2) in working circuits and largest SRAM array (364 Mbit) reported to date. Each of these SRAM chips has over 2.9 billion transistors!
I do remind students that Moore’s Law is changing. Traditional transistor scaling (where smaller dimensions alone provide improvement) has become less influential in Moore’s Law scaling. Therefore, in generations after the 130nm node (90nm, 65nm, 45nm, 32nm, 22nm etc.) performance enhancers have been added to continue to drive the transistor roadmap forward (e-SiGe and strained SiN for strain in the 90nm and 65nm nodes, and high-k metal-gate (HiK-MG) in the 45nm and 32nm nodes.
Moore’s Law and transistor scaling are not showing any sign of slowing down, but they are showing signs of changing to better meet today’s market requirements. Achieving very high operating frequencies is no longer the prime target for new microprocessors. Instead, the goal has shifted to delivering higher performance combined with lower power.“Power efficiency” is the main scaling goal for chips used both in small hand held devices and in large data centers. So, the goals have shifted a bit, and the technology options are changing over time, but the value and excitement of driving Moore’s Law remain undiminished.