32nm SOC process, getting many things right at once

A colleague of mine, upon learning that I was a pilot, wanted me to write a blog comparing flying to Intel processes used to make consumer products (these processes are SOC processes such as Intel’s 32nm SOC process, recently published at IEDM). I must confess that the analogy wasn’t immediately obvious to me, and I had to go away and think about it.

However, after thinking about it, there IS a strong analogy.   In flying, particularly in instrument flying, the big trick is to simultaneously do a large number of things correctly.   The pilot must simultaneously scan the key instruments, read the approach chart, listen to the radio, keep the plane on the proper heading, track the glideslope, lower the gear, talk to air traffic control, make sure the airport lights are on …   and … oh yes, not forget to fly the plane all the way into a smooth landing.     Just like in flying, in an SOC process the big trick is to do a very large number of things simultaneously and correctly.  

For the designer to optimize power and performance, the process needs to supply the designer with a number of different transistors.   Intel’s 32nm SOC process achieves this with high-performance (HP), low power (LP), ultra-low-power (ULP) and high voltage (HV) IO transistors.  The HP, LP and ULP transistors share the same high-k dielectric layer, and the HV IO transistors use a composite gate dielectric stack with a pre-patterned thermal oxide layer underneath the high-k layer to tolerate higher voltage stress.  The designer can use the HP transistors where performance is important, and the LP and ULP devices where power is important.  The HV devices let the designer support all those little toys we plug into our laptops. 

Just like the pilot needs to read and make decisions from the wide variety of detailed information on the approach chart, the process needs to supply a wide variety of additional “passive” elements to the designer.  These “passive” elements (resistors, capacitors and inductors) are particularly important in analog functions such as wireless communications and high-speed ethernet connections.  Intel’s 32nm SOC process supports well resistors, trench contact linear resistors, and precision linear resistors (capable of < 0.5 % matching with low TCR).  High Q inductors (Q > 20) are supported as well MIS and MOM metal finger capacitors (Q > 100).    In addition, the process supports varactors (for tuning) as well as vertical BJTs and bandgap diodes (for diode reference circuits, such as thermal sensors).  


Of course, just like the pilot needing to do all these critical things and still fly the plane into a smooth landing, the process needs to support the entire infrastructure, including back-end metals, SRAM cells, as well as provide good reliability and yield.    Intel’s 32nm SOC process achieves this by providing seven to eleven layers of metals with tighter pitch upper metal layers to improve routing density.   A thick 7 um top metal layer  is offered for on-die power distribution.  Several 6T SRAM are supported, including high density (0.148um2)  and low voltage/high performance (0.171um2) bit cells.    Healthy low Vmin and high volume manufacturing yield on these SRAM cells have been routinely collected from 291Mbit test chips.

 

Just like in aviation, the key takeaway is that processes (such as Intel’s 32nm SOC process) do an enormous number of things correctly to enable the next generation of SOC devices.   

 

 

5 Responses to 32nm SOC process, getting many things right at once

  1. Joseph says:

    Interesting post. I wasn’t aware that inductors were included in a chip. Perhaps it hinges on the question: what does SoC stand for? Pardon my ignorance. “System-on-a-chip?” In which case I guess the inductors make sense.

  2. Kelin Kuhn says:

    You are absolutely correct. SOC means system-on-a-chip. Inductors are useful both in SOC applications (for example, putting radios on chip). However, inductors are also useful for some non-SOC mainstream applications. For example designers of PLLs (phase-locked-loop) circuits, frequently used for timing, are researching using LC PLLs (with both inductors and capacitors) in order to reduce jitter in comparison with the older style of PLL (which didn’t need an inductor).

  3. Saurabh says:

    Thanks for the article, interesting read. From your above comment I gather that designers of PLLs are researching using LC inductors in order to reduce jitter. Are they considering using LC voltage controlled oscillators instead of active components to reduce noise from power supply variation? Or in some other part of the PLL, though I can’t really think of where else it could be used.