With today’s launch of the all new 2010 Intel® Core Processor Family (based on Westmere, code name for our 32nm project), this is a great time to discuss the the 32nm process technology (and the semiconductor communities response to this technology!)
Traditionally, Intel presents the details of its process technologies at the International Electron Devices meeting (IEDM) and 32nm is no exception. Although I was unable to attend the conference this year, my colleagues (and the faithful blogosphere) have provided me with an opportunity to tell the real story.
The 32nm process technology is based on high-k metal gate. Intel was the first manufacturer to introduce the high-k metal gate technology into manufacturing in 45nm (see IEDM 2007) and (as Carl Wintgens from EE times points out) “Semiconductor Insights has yet to observe a metal gate technology in a commercial device from any other semiconductor manufacturer.”
Like Intel’s 45nm technology, Intel’s 32nm high-k metal gate process is a gate-last (or replacement gate process). The gate-last (or replacement gate) architecture provides a higher thermal budget for the midsection (better activation of S/D anneals), lower thermal budget for the metals (improved range of metal choices) AND delivers significant improvement of strain for both NMOS and PMOS. The metal gate (and associated strain) gives these transistors more performance at the same power, to enable your favorite performance-hungry applications (things like games, video editing and so on).
The high-k metal gate process in 32nm generated some big headlines in the blogsphere. David Lammers of Semiconductor International reported the big news, as “Intel’s flagship 32 nm technology achieved record drive current levels, with the PMOS transistor showing a 35% drive current improvement over the 45 nm PMOS device.” Lammers also picked up a subtle but key aspect of 32nm as he pointed out “For the first time, linear drive currents on the PMOS have overtaken NMOS.” It will only be a short time before saturated drive currents on PMOS overtake NMOS (perhaps at 22nm?). Matched drive currents on NMOS and PMOS permit the best possible layout density (thus lower cost!) and have been a “wish-list” item from designers for decades.
There has been much discussion on gate first vs gate last (or replacement gate) since Intel’s initial introduction of replacement gate in 45nm. However, as David Lammers from Semiconductor International reports, Intel’s vision on gate last is finally being appreciated. Lammers headline says a great deal with, “Problems with the gate-first approach to high-k/metal gate deposition may force IBM to switch to the gate-last approach pioneered by Intel.” Lammers adds, “Concerns about threshold voltage shifts and other performance problems with the gate-first approach to high-k/metal gate creation may cause GlobalFoundries (Sunnyvale, Calif.) and other members of the IBM-led Fishkill Alliance to shift to a gate-last technique, sources said at the International Electron Devices Meeting (IEDM), going on this week in Baltimore [IEDM 2009].” In addition, Lammers reports, “”The baseline roadmap at TSMC is gate last,” said Jack Sun, in charge of technology strategy at TSMC.”
Of course, the most important point illustrated by 32nm is that it continues to maintain Moore’s law scaling! Carl Wintgens from EE times takes the stance that Moore’s Law is alive an well, with “All three players [i.e. Intel, AMD, TSMC] had comparable critical dimensions, illustrating that Moore’s law is alive and well with no sign of slowing.” Lammers from Semiconductor International was slightly more pessimistic with, “Though several participants at IEDM said CMOS scaling is likely to slow to a three-year pace, Bohr said Intel plans to stay on a two-year cadence.”
As a closing thought, Carl Wintgens from EE times highlights Intel’s continued commitment to driving innovation with “Intel clearly shows leadership in implementing process innovations”
For a look at the detailed IEDM technical papers showcasing these neat features, check out the links below!
32nm at IEDM 2009: Paper
32nm at IEDM 2008: Foils and Paper and David Kantor at Real World Technologies 2008 article
Next month, the 32nm future is system-on-chip (SOC)!