Massive cache for 8-core processor designed for high performance, low power and high yield

posted by esther andrews on July 20, 2009

Intel recently described a 24MB 24-way set associative 8-ported 3rd level cache for an upcoming 8-core Intel® Xeon® Processor with design emphasis on high density, low power and design reuse. It features a 0.3816 ?m2 bit cell in a 45nm high-k metal gate technology using 9 copper interconnect layers. Sleep transistors are used extensively to minimize the leakage power. A shutoff option is available to eliminate the leakage power in disabled portions of the cache. Fine-grained clock gating is implemented to reduce dynamic power. A separate power supply for the cache allows it to be run at the lowest operating voltage to minimize power consumption while meeting the frequency target. During shutoff, the power supply of the SRAM can be as low as 0.36V, which saves approximately 83% of leakage power. There is an extensive redundancy scheme to ensure the manufacturability of the processor. Together, these features enable Intel to produce a massive 45nm cache, which in turn enables a very high performance, yet also very energy-efficient, Intel Xeon processor. Details were presented recently at the 2009 VLSI Circuits Symposium in Kyoto, Japan.

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11 Responses to Massive cache for 8-core processor designed for high performance, low power and high yield

  1. Sundar Srinivasan says:
    July 20, 2009 at 9:01 pm

    Intel Itanium 2 (Montecito) processor featured a 24MB L3 cache in 90nm. Is this L3 cache similar to that, but with smaller feature size thanks to high-k metal gate? I am interested in knowing more detail. Could you please send a link to the actual paper presented? Thanks.

  2. Esther Andrews says:
    July 22, 2009 at 4:05 pm

    The smaller feature size is due to the smaller SRAM cell size. (High-k metal gate lowers leakage.) Contacting you to provide you with the paper presented at the VLSI Symposium.

  3. krishnadas says:
    July 28, 2009 at 7:26 am

    Would like to go through the paper presented.

  4. Josh P @ UCF says:
    July 28, 2009 at 1:54 pm

    Very impressive.

  6. (w) says:
    August 3, 2009 at 12:54 am

    Hi, looks interesting, can I also have the presentation paper, please? Thanks :) .

  7. Douglas Sherwood says:
    August 7, 2009 at 7:05 am

    Very cool, just what I was waiting for.
    I too would like more info regarding this.

  8. R says:
    August 11, 2009 at 2:41 am

    Interesting. I heard there was information about 32 nm technology as well. Was it in this conference? Would like to take a look at the presentation paper if possible. Thanks…

  9. Esther Andrews says:
    August 11, 2009 at 8:01 am

    For the latest on 32nm, you can go to http://www.intel.com/technology/architecture-silicon/silicon.htm?iid=tech_as+silicon_head. I’ll send paper via email.

  10. Jeff says:
    August 11, 2009 at 4:19 pm

    Hi Esther, this paper sounds great! Would you be so kind to forward to me? Thanks!

  11. zin says:
    September 12, 2009 at 6:37 am

    we are waiting for monster server that can handle 128 thread at one computer
    i hope intel have release that ASAP
    with good price :)