Intel recently described a 24MB 24-way set associative 8-ported 3rd level cache for an upcoming 8-core Intel® Xeon® Processor with design emphasis on high density, low power and design reuse. It features a 0.3816 ?m2 bit cell in a 45nm high-k metal gate technology using 9 copper interconnect layers. Sleep transistors are used extensively to minimize the leakage power. A shutoff option is available to eliminate the leakage power in disabled portions of the cache. Fine-grained clock gating is implemented to reduce dynamic power. A separate power supply for the cache allows it to be run at the lowest operating voltage to minimize power consumption while meeting the frequency target. During shutoff, the power supply of the SRAM can be as low as 0.36V, which saves approximately 83% of leakage power. There is an extensive redundancy scheme to ensure the manufacturability of the processor. Together, these features enable Intel to produce a massive 45nm cache, which in turn enables a very high performance, yet also very energy-efficient, Intel Xeon processor. Details were presented recently at the 2009 VLSI Circuits Symposium in Kyoto, Japan.
Connect With Us
Popular Tags@ces-meta @idf08 @page-included-content Atom CES CES 2008 Core Core 2 Duo demo design desktop ethnography extensions graphics IDF IDF2007 IDF2008 innovation Intel Intel Atom Intel CES Intel Developer Forum Lithography MacBook Marc Wallis MID mids mobile Mobile Devices Mobile World Congress mobility Nehalem nettops new brand quad core Silverthorne Technologies for our Lives technology transistor TRIZ UMPC video WiMAX Wireless Xeon