Massive cache for 8-core processor designed for high performance, low power and high yield
posted by Esther Andrews on July 20, 2009
Intel recently described a 24MB 24-way set associative 8-ported 3rd level cache for an upcoming 8-core Intel® Xeon® Processor with design emphasis on high density, low power and design reuse. It features a 0.3816 μm2 bit cell in a 45nm high-k metal gate technology using 9 copper interconnect layers. Sleep transistors are used extensively to minimize the leakage power. A shutoff option is available to eliminate the leakage power in disabled portions of the cache. Fine-grained clock gating is implemented to reduce dynamic power. A separate power supply for the cache allows it to be run at the lowest operating voltage to minimize power consumption while meeting the frequency target. During shutoff, the power supply of the SRAM can be as low as 0.36V, which saves approximately 83% of leakage power. There is an extensive redundancy scheme to ensure the manufacturability of the processor. Together, these features enable Intel to produce a massive 45nm cache, which in turn enables a very high performance, yet also very energy-efficient, Intel Xeon processor. Details were presented recently at the 2009 VLSI Circuits Symposium in Kyoto, Japan.
Comments (11)
tagged: cache, cpu, performance, processor, server, transistor, Xeon
Comments
Jul 20 | Sundar Srinivasan said:
Intel Itanium 2 (Montecito) processor featured a 24MB L3 cache in 90nm. Is this L3 cache similar to that, but with smaller feature size thanks to high-k metal gate? I am interested in knowing more detail. Could you please send a link to the actual paper presented? Thanks.
Jul 22 | Esther Andrews said:
The smaller feature size is due to the smaller SRAM cell size. (High-k metal gate lowers leakage.) Contacting you to provide you with the paper presented at the VLSI Symposium.
Jul 28 | krishnadas said:
Would like to go through the paper presented.
Jul 28 | Josh P @ UCF said:
Very impressive.
Jul 28 | Esther Andrews said:
Paper forwarded.
Aug 03 | (w) said:
Hi, looks interesting, can I also have the presentation paper, please? Thanks :).
Aug 07 | Douglas Sherwood said:
Very cool, just what I was waiting for. I too would like more info regarding this.
Aug 11 | R said:
Interesting. I heard there was information about 32 nm technology as well. Was it in this conference? Would like to take a look at the presentation paper if possible. Thanks…
Aug 11 | Esther Andrews said:
For the latest on 32nm, you can go to http://www.intel.com/technology/architecture-silicon/silicon.htm?iid=techas+siliconhead. I’ll send paper via email.
Aug 11 | Jeff said:
Hi Esther, this paper sounds great! Would you be so kind to forward to me? Thanks!
Sep 12 | zin said:
we are waiting for monster server that can handle 128 thread at one computer i hope intel have release that ASAP with good price :)