posted by Jeff Galinovsky on July 31, 2009
I had the pleasure of attending a cool event a the California Academy of Science that brought a bit of Science, a bit of Technology, and a bit of fun kid chaos! Intel sponsored a Summer Tech Day event here that brought in a handful of press and Intel, their kids, and a bunch of Intel-powered classmate PCs for some cool activities. (See the live Twitter feed) So all the kids in attendance, including my 10 year old daughter Mackenzie, got to use a classmate PC to run through an organized curriculum of science explorations. They got a bit of training before they embarked by myself and Mackenzie on how to use the classmates and how they were going to use them in the exhibit. Then they were off in groups led by docents.
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tagged: California, Classmate PC, education, science
posted by Jeff Galinovsky on July 31, 2009
Ok - I have been wanting to do this for some time now, and finally have started with this post! I will be blogging about Education Technology issues and also about how Intel powered classmate PCs can help solve some of those issues where relevant. I am very passionant about education and how we can transform the way we teach kids through the use of technology so follow me on a fun journey into the Education Technology space!
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tagged: Classmate PC, education
posted by Esther Andrews on July 20, 2009
Intel recently described a 24MB 24-way set associative 8-ported 3rd level cache for an upcoming 8-core Intel® Xeon® Processor with design emphasis on high density, low power and design reuse. It features a 0.3816 μm2 bit cell in a 45nm high-k metal gate technology using 9 copper interconnect layers. Sleep transistors are used extensively to minimize the leakage power. A shutoff option is available to eliminate the leakage power in disabled portions of the cache. Fine-grained clock gating is implemented to reduce dynamic power. A separate power supply for the cache allows it to be run at the lowest operating voltage to minimize power consumption while meeting the frequency target. During shutoff, the power supply of the SRAM can be as low as 0.36V, which saves approximately 83% of leakage power. There is an extensive redundancy scheme to ensure the manufacturability of the processor. Together, these features enable Intel to produce a massive 45nm cache, which in turn enables a very high performance, yet also very energy-efficient, Intel Xeon processor. Details were presented recently at the 2009 VLSI Circuits Symposium in Kyoto, Japan.
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tagged: cache, cpu, performance, processor, server, transistor, Xeon
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