posted by Nick Knupffer on June 22, 2007
As you may have seen in the media, Intel recently hosted its annual R&D day here in Santa Clara. The R&D day is a futuristic showcase introduced by CTO Justin Rattner, followed by roomfuls of various exhibits based on the research of Intel’s Corporate Technology Group (CTG).
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tagged: Dynamic Physical Rendering, ray tracing, terascale
posted by Nick Knupffer on June 22, 2007
Intel recently held a press briefing in San Francisco outlining future Itanium plans. Chief among the nuggets of information where the following revelations:
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tagged: 32nm, Itanium, RISC, Tukwila
posted by Nick Knupffer on June 20, 2007
There is a lot of talk right now about 45nm – the newest and most exciting step along the Moore’s Law story. (Yes, it IS exciting…)
Essentially it means that transistors can be made smaller, and the smallest feature size is only 45nm across, that is less than 200 silicon atoms wide.
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tagged: 45nm, Gordon Moore, high-k, metal gate, Moore's Law, silicon, transistor
posted by Pat Gelsinger on June 15, 2007
I get asked regularly about Intel’s Itanium strategy and plans.
Having taken over responsibility for Itanium at Intel in 2005, I spent time taking a deep and careful look at the technology, products and positioning of the product in the market place and what was required to make it successful.
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tagged: Dual-Core, Itanium, Montecito, Montvale, Poulson, Tukwila, Xeon
posted by Stacy English on June 11, 2007
Science gurus Adam Savage and Jamie Hyneman show how Intel’s incredible shrinking transistors are helping to cram old, super-sized supercomputer performance into small, sleek laptops built with Intel Centrino Duo processor technology. This video was created to celebrate the introduction of Intel Centrino Duo and Intel Centrino Pro processor technology in May 2007.
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tagged: Centrino, Centrino Duo, transistor
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