The deep power down state (aka C6) is another interesting and unique feature. We save away the entire processor state for the cores and turn off the caches and put the cores in an extremely low power state. This significantly reduces processor power consumed in idle mode and extends battery life. The OS initiates this with an MWAIT instruction and the CPU works with the chipset VRM to enter the deep power down state. On a wake up event (interrupt), voltage is increased, clocks and CPU state restored and execution begins.Too frequent transitions to deep power down state can result in energy loss and reduced battery life. The Penryn processor supports intelligent heuristics to recognize when Deep Power Down energy cost is greater than the idle period savings and it demotes OS Deep Power Down requests to C4 state. To see Steve Fischer’s IDF presentation go to https://intel.wingateweb.com/published/BMAS004/BMAS004_100Eng.pdf Feel free to post your questions here or on my original post.
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