The black and white worlds of 802.11a/b/g Wi-Fi are giving way to shades of gray with 802.11n. The days of simply knowing that the laptop you were going to buy included the latest Wi-Fi adapter are gone. 802.11n is dramatically different than its 802.11 Wi-Fi predecessors. It’s the first multidimensional Wi-Fi specification that makes product comparisons challenging. You need to dig deeper before you buy 802.11n Wi-Fi products.
What makes 802.11n different is the specification’s support of multiple radios and antennas that can transmit/receive multiple data streams - called spatial streams. In 802.11n vernacular, these send and receive antenna configurations are noted as 1x1, 1x2, 2x2, or 3x3. These numbers indicate how many transmit and receive antennas and radios are in an 802.11n access point (AP) or client. They determine how many different spatial streams of data can be sent at one time to improve signal reception.
More antennas and streams mean faster speeds, less dead zones, fewer dropped connections, and better coverage. 802.11n 1x1 Wi-Fi adapters don’t take advantage of 802.11n’s multi-stream capabilities so they can only reach a maximum data rate of 72 Mbps. A 1x2 802.11n adapter with two receive streams can double the maximum data rate to 150 Mbps. Take it up to 3x3, the maximum data link can reach 450 Mbps.
Choosing the right 802.11n solution is not only about speed, it’s also about more reliability and range in your Wi-Fi connections. Check out this new animation that shows the power of 802.11n multiple data streams vs. single stream 802.11a/b/g/n Wi-Fi.
I get excited when my PC can solve problems for me. Figuring out a new way to communicate information or different ways to connect with friends and family add to the quality of my work and life. While we all instinctively understand these small but significant contributions, we often don’t think about the bigger contributions computing is making to society. Well, that is until you speak to someone like Lorie Wigle, GM of Intel’s Eco-Tech program office. Lorie stopped by to chat about her recent trip to Copenhagen where she represented Intel at the global climate conference. We talked about moving from a focus strictly on climate change mitigation to one that includes adaptation and discussed why technology innovation is at the heart of the world’s efforts to address the massive issues we’re facing.
Ironically my iTunes went straight to Madonna’s “Material Girl” after first listening to the interview with Lorie which made me reflect on how we may have gotten into this situtation to begin with. It also reminded me of one of the greatest promises of technology: the “de-materialization” of the stuff we want and need towards a a society where information replaces use. If you’d like to learn from Intel’s De-Material girl, check out the interview.
For those of you who attended CES earlier this month or simply followed the news from that event, you may have heard below the noise of streaming TV boxes and Intel Readers a fairly major announcement from Intel…the release of our first 32nm products (27 of them, aimed at the desktop and mobile market segments). While this tick tock thing is getting so finely tuned it almost becomes an expectation, I wanted to take a step back and once again celebrate that delivering this “first in the world” technology, if you get down to it, seems a bit like high tech wizardry. After all, 32nm (for those who aren’t working in these small sizes all the time) represents about 200 atoms in width, and about 60 million transistors of this type fit on the head of a pin. I wanted to learn more about this wizardry so went to speak to Mr. Wizard himself, Mark Bohr, Intel’s Senior Fellow in charge of ensuring that Intel continues to deliver upon the tick tock model. Mark talked about the challenges of continued delivery of ever smaller designs and unveiled a bit about the hard core science that goes on behind all of this magic. He briefly looked forward to his organization’s current challenge, 22nm, and gave a look back to the major breakthrough his team made to deliver high K metal gates at 45nm. Mark got pretty excited when asked about 45nm, and you can understand the excitement when you realize that Moore himself (yes that Moore) called it “The biggest change in transistor technology in 40 years”. Enjoy the interview.
With this new mobile device, you can take a picture of printed material, like a book or restaurant menu, and it reads it aloud to you. It combines an Intel® Atom™ processor, camera, optical-character-recognition and text-to-speech into a small package that makes it as simple as “point, shoot and listen” (video) (features/specs).
Such an honor is quite an accomplishment for any consumer product, but for an assistive device to receive these awards is particularly remarkable.
The placement of my HDTV in the family room was never designed to let me hook up a
laptop to it. It’s as if my HDTV and my Internet fed laptop were in parallel digital universes. Sure, I could sit on the couch with my laptop and run a long HDMI cable across the room, but a cord laying across the floor is fraught with danger.
Then came the “Big Bang” at CES 2010 with the announcement of Intel® Wireless Display (aka “WiDi”). I so get this product. With Intel® Wireless Display and a laptop powered by select all new 2010 Intel® Core™ processors and an Intel® Centrino® Wi-Fi adapter, I just sit back and experience my favorite videos, photos, music or any content projected onto my HDTV. No wires, no additional remote control, it’s all done via Wi-Fi. I don’t even need to mess with my Wi-Fi access point thanks to Intel® My WiFi Technology, which creates a Wi-Fi Personal Area Network (PAN). Finally, the Internet hits the big screen without wires!
On Jan. 17 laptops by Dell, Sony and Toshiba and a TV adapter by NETGEAR - featuring Intel® Wireless Display - will be available at Best Buy* in the United States and Canada as part of its Blue Label 2.0 program.
I was overwhelmed by the interest received on my initial post on Light Peak a few months ago. Plenty of questions and ideas were raised on the potential of a single IO port for multiple protocols and support for power; all over an optical connector. Clearly there is a lot of excitement surrounding high speed optics, and the many benefits that can come to compute platforms we all use today.
With that said, I wanted to bring Light Peak up for some discussion again as it has just been demonstrated in Paul Otellini’s keynote at CES ‘10 as a link for high bandwidth 3-D video. I thought it might be a good time to provide an update on where Light Peak stands, and share a little bit more information.
So what’s New?
In the few months since Intel Developer Forum (IDF), we have been able to show an integration of Light Peak modules into a desktop system and monitor. At IDF the solution we were showing was an engineering version which was an early engineering prototype. One of the important things about Light Peak, in addition to high speed and multi-protocol support, is its ability to reach consumer form factors, and at CES we are showing how a standard normal form factor system can be equipped with this technology.
Additionally, as we move forward with the industry to ensure that Light Peak will evolve into a well supported standard, we have some additional supporters for the technology to help drive the vision and success of the technology. More announcements of support as well as standards activities will be coming over the coming months and quarters, but progress continues!
Driving a new IO technology standard will take time, but it’s key to make sure the final solution will meet the industries needs both from a cost and feature standpoint.
In other news, an exciting development for Light Peak was the announcement by PC Magazine that Light Peak won a technical excellence award for 2009. Very exciting!
Hopefully, many of you reading had a chance to attend CES and see Light Peak silicon in action, but for those who didn’t, please see the link below for more information.
The Intel® Centrino® brand now represents Intel’s wireless products, targeting a broader range of users than ever before. Three new Intel® Centrino® Wireless adapters feature advanced 802.11n multi-stream capabilities and dual-band support for Wi-Fi, offering users up to 8 times greater speed, consistent coverage and connectivity while consuming minimal power. This is more than just a name change, the Intel® Centrino® Wireless product lineup becomes available across the broad range of Intel processors from Intel® Atom™ to Intel® Core i7™. All adapters support Intel® My WiFi Technology, which allows users to turn their laptop into a virtual hotspot to directly connect to Wi-Fi devices.
With today's launch of the all new 2010 Intel® Core Processor Family (based on Westmere, code name for our 32nm project), this is a great time to discuss the the 32nm process technology (and the semiconductor communities response to this technology!)
Traditionally, Intel presents the details of its process technologies at the International Electron Devices meeting (IEDM) and 32nm is no exception. Although I was unable to attend the conference this year, my colleagues (and the faithful blogosphere) have provided me with an opportunity to tell the real story.
The 32nm process technology is based on high-k metal gate.Intel was the first manufacturer to introduce the high-k metal gate technology into manufacturing in 45nm (see IEDM 2007) and (as Carl Wintgens from EE times points out) "Semiconductor Insights has yet to observe a metal gate technology in a commercial device from any other semiconductor manufacturer."
Like Intel's 45nm technology, Intel's 32nm high-k metal gate process is a gate-last (or replacement gate process).The gate-last (or replacement gate) architecture provides a higher thermal budget for the midsection (better activation of S/D anneals), lower thermal budget for the metals (improved range of metal choices) AND delivers significant improvement of strain for both NMOS and PMOS. The metal gate (and associated strain) gives these transistors more performance at the same power, to enable your favorite performance-hungry applications (things like games, video editing and so on).
The high-k metal gate process in 32nm generated some big headlines in the blogsphere. David Lammers of Semiconductor International reported the big news, as "Intel's flagship 32 nm technology achieved record drive current levels, with the PMOS transistor showing a 35% drive current improvement over the 45 nm PMOS device."Lammers also picked up a subtle but key aspect of 32nm as he pointed out "For the first time, linear drive currents on the PMOS have overtaken NMOS." It will only be a short time before saturated drive currents on PMOS overtake NMOS (perhaps at 22nm?). Matched drive currents on NMOS and PMOS permit the best possible layout density (thus lower cost!) and have been a "wish-list" item from designers for decades.
There has been much discussion on gate first vs gate last (or replacement gate) since Intel's initial introduction of replacement gate in 45nm.However, as David Lammers from Semiconductor International reports,Intel's vision on gate last is finally being appreciated.Lammers headline says a great deal with, "Problems with the gate-first approach to high-k/metal gate deposition may force IBM to switch to the gate-last approach pioneered by Intel."Lammers adds, "Concerns about threshold voltage shifts and other performance problems with the gate-first approach to high-k/metal gate creation may cause GlobalFoundries (Sunnyvale, Calif.) and other members of the IBM-led Fishkill Alliance to shift to a gate-last technique, sources said at the International Electron Devices Meeting (IEDM), going on this week in Baltimore [IEDM 2009]." In addition, Lammers reports, ""The baseline roadmap at TSMC is gate last," said Jack Sun, in charge of technology strategy at TSMC."
Of course, the most important point illustrated by 32nm is that it continues to maintain Moore's law scaling!Carl Wintgens from EE times takes the stance that Moore's Law is alive an well, with "All three players [i.e. Intel, AMD, TSMC] had comparable critical dimensions, illustrating that Moore's law is alive and well with no sign of slowing."Lammers from Semiconductor Internationalwas slightly more pessimistic with,"Though several participants at IEDM said CMOS scaling is likely to slow to a three-year pace, Bohr said Intel plans to stay on a two-year cadence."
As a closing thought, Carl Wintgens from EE times highlights Intel's continued commitment to driving innovation with "Intel clearly shows leadership in implementing process innovations"
For a look at the detailed IEDM technical papers showcasing these neat features, check out the links below!
The Intel "Doodle" advertisement went public recently.While an actress plays me (the idea is the actress is younger, prettier and taller than I am J) the doodles are mine and capture technical highlights of various Intel projects I've been involved with.There has been significant curiosity about the Doodle itself and so I've given a couple of talks recently to "unpack" the Doodle for interested audiences (a hyperlinked version of these talks is at http://www.intel.com/pressroom/kits/advancedtech/ scroll down to the doodle and click on the pictures for a discussion of each one).
In giving these talks, I am continually reminded of the importance of mobility enhancement in Intel's long term technical roadmap.(Remember that transistor drive current is directly proportional to mobility, and so any improvement in mobility is a 1 for 1 improvement in drive current and thus performance).
Another option for mobility enhancement is using a different Si substrate orientation (for example, 110 vs 100). This is more complex than it sounds, as NMOS is better on 100 and PMOS is better on 110, and both cannot exist on the same simple (read cheap!) wafer. A critical question with this approach is just how much the PMOS improves and the NMOS degrades - because, if the NMOS degradation is small enough, this is still worth doing (see P. Packan at IEDM 2008, http://www.intel.com/pressroom/kits/advancedtech/ieee/Strained_IEDM2008_ppt.htm and http://www.intel.com/pressroom/kits/advancedtech/ieee/Strained_IEDM2008_doc.htm ).Now, it IS possible to fabricate the NMOS transistor horizontally and the PMOS transistor vertically to get the optimal orientation in both cases.The issue here is process and design rule complexity (i.e. high cost!).Another alternative (for example, the IBM HOT process) is to integrate both crystal orientations on the same wafer. The issue here is ... HIGH COST!
A longer term option is replacement of silicon by new channel materials (for example, Ge or III-V materials). Note that while replacing the entire wafer with Ge or III-V is incompatible with modern 300mm manufacturing, replacing only the channel with Ge or III-V materials is a potentially manufacturable approach.
While Ge is a very well known semiconductor (the first transistors were made of Ge!), the concern with Ge is that its native oxide (GeO) is a poor thermally unstable oxide. A fascinating option is to make Ge transistors with HiK dielectrics rather than GeO - however, this is not a trivial challenge! Even today, there is no known method for fabricating thin (say 1nm EOT) high mobility dielectrics on Ge (literature results reporting exceptional mobilities are from thick gates).Another issue is the narrow bandgap of Ge, which increases band-to-band tunneling and results in higher standby leakage (Ioff).Still another issue is the lattice mismatch between Si and Ge; which can result in various defects and dislocations.
III-V materials are both more challenging and have more potential than Ge.As with Ge, integration of gate dielectrics is a major challenge.As with Ge, the low Eg III-V materials (ex: InAs, InSb, Ge) are subject to standby leakage (Ioff) increases due to band-to-band tunneling (and the effect worsens with strain).The very high mobility materials (ex: InAs, InSb) have low density of states in the gamma-valley, resulting in reduced drive currents.Last, but not least,III-V materials are also lattice mismatched to Si, creating various defects and dislocations.However, in spite of these challenges, Intel has recently reported integration of a composite high-k gate stack on InGaAs (see M. Radosavljevic, IEDM 2009, link pending) as well as the major milestone ofimproved low power performance of III-V over Si for the voltage range of 0.5-1V (see G. Dewey, IEDM 2009, link pending).
Stay tuned, next month - IEDM, 32nm and what that means for the all new 2010 Intel® Core Processor Family
del.icio.us