Results tagged “terascale”
Investing in hardware for parallel programmability
posted by Jim Held on March 23, 2009 at Research@Intel
About a year ago, Intel and Microsoft each invested $10M in jointly funding Universal Parallel Computing Research Centers at UC Berkeley and U of Illinois to make parallel programming mainstream in future client software. I’ve had the pleasure of attending...
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tagged: parallel programming, software development, terascale, UPCRC
Towards virtual dressing rooms
posted by Sean Koehl on March 18, 2009 at Research@Intel
This past month I took part in a technology showcase that we held in New York City to introduce the media to some innovations on the horizon that we think will change the lives of everyday people - not just...
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tagged: body tracking, Immersive Connected Experiences, physical modeling, shopping, terascale, virtual worlds
Real-time ray tracing applied to Quake Wars
posted by Daniel Pohl on January 23, 2009 at Research@Intel
Last year at the Research at Intel day we demoed a ray traced version of “Enemy Territory: Quake Wars” for the first time. Two month later at the Intel Developer Forum in San Francisco we showed an enhanced and faster...
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tagged: ray tracing, terascale
Madeleine Glick on Polymer waveguides for high speed board-level optical interconnects
posted by Guest Blogger on May 05, 2008 at Research@Intel
The continued growth of data rates in servers, routers and high-bandwidth computing systems has led to an increased interest in optical backplanes for these applications. Data rates in the backplane are increasing to several Gbps/channel and higher. The trend to...
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tagged: optics, polymer, research, silicon photonics, terascale
Yimin Zhang on Why do we need many-core?
posted by Guest Blogger on March 31, 2008 at Research@Intel
Now we are already in a Multi-core era, dual-core has become mainstream, and some people even have Quad-core CPUs in their desktop PC. But some people still are are not clear if, in the future more cores will benefit them,...
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tagged: IDF, IDF2008, intel, many core, model-based computing, multicore, research, terascale
Introducing two “Universal Parallel Computing Research Centers”
posted by Justin Rattner on March 19, 2008 at Research@Intel
Today, it’s a pleasure for me to report that Intel and Microsoft are joining forces to accelerate the mainstream adoption of highly parallel computing technology. Together, the two companies are pioneering the concept of industry-funded “Universal Parallel Computing Research Centers”...
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tagged: IDF, IDF2008, intel, parallel computing, parallel programming, research, terascale
"Automated sports highlights" demo video
posted by Sean Koehl on March 17, 2008 at Research@Intel
I wanted to share a video of some of the application research we have going on at our Intel China Research Center in the area of video mining. In collaboration with Tsinghua University, Yimin Zhang and his team at ICRC...
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tagged: China, ICRC, parallel programming, research, soccer, terascale
Designing future computers with future workloads
posted by Timothy Mattson on February 26, 2008 at Research@Intel
What will people do with their computers in five, ten or twenty years? How will computers need to change to support these future usage models? And finally, how the heck are we going to program these things? These are the...
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tagged: many core, parallel programming, PARSEC, terascale
Randy Mooney on ISSCC: Scaling performance/watt through circuit innovation
posted by Guest Blogger on February 03, 2008 at Research@Intel
As we look forward to enabling exciting new opportunities in platforms ranging from mobile computing to the data center, along with associated new applications, one common denominator of all these products will be the underlying process technology and the circuits...
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tagged: accelerators, circuits, DRAM, interconnect, ISSCC, memory, SRAM, terascale
What real physics can do for animation (video)
posted by Sean Koehl on January 25, 2008 at Research@Intel
Check this video out. These are special effect animations using physical modeling techniques, devloped Prof. Ron Fedkiw’s group at Stanford (see Jerry’s previous blog). Intel collaborates with Ron’s group to parallelize, analyze, and scale the performance of Prof. Fedkiw’s PhysBAM,...
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tagged: physical modeling, terascale
Resiliency – A Key Strategy to Keep Reaping the Benefits of Moore’s Law (guest post)
posted by Guest Blogger on December 27, 2007 at Research@Intel
This post comes from Antonio Gonzalez, director of the Intel Barcelona Research Center in Spain. His lab conducts a variety of research aimed at improving the performance and energy efficiency of future multi-core and tera-scale microprocessors. His post relates to...
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tagged: microprocessor, resilient architectures, Spain, terascale, variability
The Problem(s) with GPGPU
posted by Anwar Ghuloum (葛安华) on October 18, 2007 at Research@Intel
Hundreds of GigaFLOPs are available in your PC today….in fact, you might even have a TeraFLOP in there. As someone who cut his teeth on a Cray C90 (15 GFLOPS max), this is an intriguing opportunity to dabble; for the...
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tagged: multi-core, parallel applications, parallel architectures, parallel programming, terascale
Rattner's Virtual World's Keynote: Research Reflections on IDF Day 3
posted by Sean Koehl on September 21, 2007 at Research@Intel
Thursday, our CTO Justin Rattner gave a keynote on virtual worlds and the emergence of what he called the 3D Internet. The 3D Internet Rattner described is the mushrooming social world of multiplayer online games, of complex animations for medicine...
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tagged: Intel, Rattner, research, terascale, virtual worlds
Tera-scale Demos at IDF
posted by Sean Koehl on September 20, 2007 at Research@Intel
Following up on Brian’s post yesterday, here’s some pics and info on the Tera-scale demos we have here at IDF....
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tagged: 80-core, Ct, IDF, Intel, ray tracing, research, terascale
Tera-scale for laptops?
posted by Sean Koehl on September 11, 2007 at Research@Intel
Recently I was looking over some slides by Intel Fellow Vivek De, which he has put together for his Intel Developer Forum session next week on “Energy Management Innovations for Future Multi-Core Processors.” In the presentation I saw a few...
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tagged: heterogenous cores, Intel, multi-core, research, terascale, viterbi
Making “virtual” more real
posted by Jerry Bautista on September 10, 2007 at Research@Intel
Within the Intel labs we were shocked by the public reaction to our 80 core disclosure last spring. The interest level was astounding, but after the initial discussions (around core type, how they were arranged/interconnected, power vs. teraflops, and the...
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tagged: 80-core, Intel, multi-core, physical modeling, research, Stanford, terascale, virtual worlds
The Many Flavors of Parallelism
posted by Anwar Ghuloum (葛安华) on August 17, 2007 at Research@Intel
In my last blog, I described why parallel programming is hard. In the next few blogs, I’ll start to describe how we’re trying to make it easy (there’s tons of good work at Intel on this). When I first started...
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tagged: data parallel, programming models, task parallel, terascale
Multi-core research update: the intimate coupling of software & hardware
posted by Sean Koehl on August 14, 2007 at Research@Intel
This week we are excited to share further technical progress towards our vision to enable scalable, programmable multi-core architectures based on many cores. We are disclosing 8 technical papers from our Tera-scale program via the Intel Technology Journal with new...
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tagged: applications, benchmark, Intel, model-based computing, multi-core, parallel programming, run-times, task scheduling, terascale, workloads
A follow-up on the the 40G Modulator
posted by Ansheng Liu on August 08, 2007 at Research@Intel
First of all, I’d like to thank every one for sending their comments to my blog “Announcing 40 Gb/s silicon optical modulator.” I will take this opportunity to try to address some of the issues raised in your comments....
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tagged: 40G, modulator, research, silicon, silicon photonics, terascale
What Makes Parallel Programming Hard?
posted by Anwar Ghuloum (葛安华) on August 03, 2007 at Research@Intel
One of the challenges of multi-core and tera-scale architecture is how to make parallel programming “easier”. But what makes it hard in the first place? I thought it might be worth explaining some of our experiences with this as a...
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tagged: bugs, parallel programming, software development, terascale
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