At the Spring 2009 Intel Developer Forum (IDF) in Beijing, Intel premiered a prototype demonstrating Group Scheduling, a technology to increase the capacity of VoIP in 802.16m, next-generation WiMAX networks. At IDF we demonstrated the reduction in size of the DL-MAP (management overhead information) for VoIP traffic with group scheduling. Here we demonstrate how the reduction in the MAP overhead leads to capacity gains, thereby supporting larger number of VoIP calls in next-gen WiMAX networks.
This is my third time being at the Research@Intel Day. Every year Intel highlights the great research projects showing off futuristic technology that could make it one day into your office or even your living room.
Imagine a future mobile experience where parents can stream their kid’s sports event live to grandparents halfway around the world with your handset. Or people can play immersive mobile games like World of Warcraft anywhere, anytime. Or enjoy true mobility for Voice and Video over IP phone calls over popular internet applications like Skype, to open up whole new opportunities for connectedness between family, friends, and colleagues. Social networks will become mobile and context-aware, multi-dimensional, and will utilize live video and highly immersive 3D Graphics, making today’s Facebook and Twitter seem like the command line interfaces of the past. Artists will collaborate real-time worldwide, and explore new frontiers of creativity. We’re taking the Internet mobile and transforming how our planet connects, whether you are a grandparent, gamer, gossip, geek, or guitar-hero!
The sponsor’s of tomorrow from Intel labs will host media and industry partners at the 8th Annual Research @ Intel Day event at the Computer History Museum to offer a preview of what is still to come for computing. More than 45 futuristic projects and concepts underway in the labs will be unveiled in the areas of the eco-technology, 3D graphics on the internet, mobility, privacy and more. Please join us live here, where we’ll broadcast Justin Rattner’s opening messages and select research demonstrations and interviews with Intel Labs very own “rock stars”.
This morning in Saarbrueken, Germany we launched a new research center at Saarland University called the Intel Visual Computing Institute. Intel has committed $12 million to this effort, which will become the newest member of Intel Labs Europe and our largest university collaboration in the region. The Intel VCI will be chartered with accelerating innovations in realistic graphics and new immersive, connected experiences such as the 3D Internet.
Since our last virtual discussion (June 2008), malware attacks continue to rise, and more so, attacks have continued to become stealthy and targeted. We have completed a key milestone for our software protection research last month; we created a research prototype of a hardware-assisted application protection capability called “Processor-Measured Application Protection Service (P-MAPS)”. The goal of this work has been to significantly reduce the Trusted Computing Base (TCB) from a full Operating System to a substantially smaller P-MAPS layer to improve the runtime security of critical applications running within the OS. The main contributions of our work are the on-demand trusted instantiation of P-MAPS and the use of P-MAPS to protect applications without interrupting the natural operation of the application or the Operating System. With P-MAPS enabled on a platform, day-0 attacks and attempts by unknown malware to attack critical applications can be mitigated.
Dynamic Software Application Protection white paper View .pdf
At Fall IDF 2008, Intel presented solutions toward realizing a vision that can accelerate secure Internet transactions by orders of magnitude. Our vision was of a world where the internet is entirely secure and attackers have no place to hide. A major step toward realizing this vision of world-wide security is making sure that all the traffic exchanged between servers and clients is encrypted. This is very difficult technical challenge since networking speeds are excessively high (10-100 Gbps), whereas cryptographic algorithms consume millions of processor cycles to execute. Since IDF, we have also worked on designing new cryptographic algorithms that can potentially offer new security/performance tradeoffs and be essential components of future computing platforms and networks. In this blog we summarize our past as well as recent accomplishments.
https://everywhere! Encrypting the Internet white paper
View .pdf
Real-time services are envisioned to be an essential component of next generation mobile broadband networks (4G), and like 2G and 3G, voice is still expected to be the most desirable service over these networks. However, mobile-broadband networks, based on IP technologies, are well-known for high packet-data efficiency, but not for voice (VoIP) efficiency. A key requirement for IEEE 802.16m, the next-generation WiMAX standard, currently under definition, is support of a large number of VoIP users. Hence, efficient support of VoIP over next-generation WiMAX is needed.
About a year ago, Intel and Microsoft each invested $10M in jointly funding Universal Parallel Computing Research Centers at UC Berkeley and U of Illinois to make parallel programming mainstream in future client software. I’ve had the pleasure of attending updates where each reported on their first year’s efforts. Clay Breshear’s blog here has a good overview of the UIUC Summit content.
One point made by both was, as the UIUC whitepaper puts it: “Hardware must be used for programmability.” For example, a UCB talk gave a plea for better performance counters and a UIUC one proposed changing the micro-architecture extensively to give programmers simpler, more easily understood parallel memory semantics.
Unfortunately, even the simplest HW modifications to increase programmability face big challenges of product costs and legacy compatibility. For example, useful as they are, performance counters are a tough sell to hard-nosed product managers. Many are intimately connected to the ‘guts’ of the processor and so are very intrusive to the design and present a big challenge to validation. That means a significant investment is required for the design and validation efforts for something that doesn’t have the direct end-user benefit of performance and other new enhancements. Of course, their use in silicon debug helps, getting the product out the door is of unquestionable value, but for that purpose not every counter has to work flawlessly, and model-specific instrumentation is fine.
The basic problem is that the customer for programmability features is not the end-user but the programmer and as one product planner facetiously commented to me: “Programmers aren’t a big market segment.” Extensive enabling of ISVs can be expensive but still more cost-effective than burdening all of 100s millions of processors shipped with the cost of features to enhance programmability.
Even so, the tuning and debug support they make possible is well recognized. We’ve continually added to and improved the performance counters since they first appeared in the original Pentium™. Architectural performance monitoring, with its commitment for consistency across micro-architectures, has appeared with Intel® Core Solo™ and Intel Core Duo™ processors.
Programmability has never been more of a concern than with today’s transition to multi-core and the need to make parallel programming mainstream. Programs that transparently scale to increasing numbers of cores are critical if multi-core is going to give ISVs the same performance progression that we enjoyed from scaling clock frequency. Lowering the bar to concurrent programs can help make more existing as well as emerging high performance applications available sooner. So, there is clear motivation to continue improvements in counters and debug features that address parallelism will continue.
But, the best way to accelerate the addition of programmability features is dual-use HW that helps at development and run-time. Some examples might be: instrumentation (performance counters) that are also needed by SW to provide outstanding QoS (quality-of-service) for multimedia, the use of replay mechanisms both for debugging and for resiliency, or ISA extensions that enable simple programming models to run faster. What are the ones that will really deliver value?
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