The first project under the collaboration is focused on the future of memory technologiesused in computing devices such as ultrabooks, laptops, tablets, and handhelds. By creating memories with much greater energy efficiency, these mobile devices will be better equipped to handle the data-intensive applications of the future. 

Our earlier collaborative work on memoryfor HPC has been very productive, so we were interested in a collaboration to explore further innovations in interconnect and memory architecture with a particular focus on mobile computing devices. 

Given that focus, our newly designated Taiwan Scientist in Residence, Dr. Wen-Hann Wang, suggested ITRI as a potential partner with close ties to industry and a proven record of making an impact with their research. For example, they helped to establish the semiconductor foundry industry with spin-outs such as TSMC. Their charter is a good match to Intel Labs, and they enjoy excellent relations with a broad cross section of the Taiwan IT industry that includes memory design houses, foundries as well as leading computing device OEMs & ODMs. Through ITRI, we may involve many of these industry players over time. 

Through Wen-Hann we connected with Dr. Cheng-Wen Wu, VP of ITRI and General Director of Information and Communications Research Labs, to set up the project which is starting under the very capable direction of our Dr. Shih-Lien Lu. 

I’m looking forward to an exciting and productive collaboration.

In computer science, “graphs” are a way to represent and explore the connections between things, such as all the stops in a subway system (pictured here for New York), all the links in a large computer network, or all the relationships between people on social networks like FaceBook. Graph computing is also used to discover meaningful correlations between events for applications such as medical informatics and cybersecurity.

However, these graph searches are challenging to compute efficiently because unlike a typical database, graphs vary wildly in size, shape and number of connections between nodes. The most interesting graph problems explore connections across large populations or massive datasets – billions of nodes with many more possible relationships between them. Drawing meaning from such “Big Data,” which could represent any type of business, scientific, or social information, is a key challenge for supercomputing and cloud computing alike. Since any node could lead to any other node (or nodes) in a vast web, it is difficult to predict which piece of data will be needed next, resulting in many trips to slower memory such as hard drives before then next computation can be performed.

Intel Architecture is well suited to graph problems because it has a cache hierarchy that is friendly to such irregular data access patterns. The challenge lies in creating the algorithms which effectively utilize this hardware.

Satish Nadathur, Jatin Chhugani, and Changkyu Kim of our Parallel Computing Lab were able to demonstrate the excellent processing power and energy efficiency of IA for the Graph500 benchmark. They achieved this result through innovative algorithm-architecture co-design which allowed the task to make much more efficient use of memory and compute on a Xeon (Westmere) cluster. Sandia Lab’s Richard Murphy, the owner of the benchmark, commended the team on an “outstanding job.”

Even more impressive than the raw performance was the efficiency of PCL’s algorithmic approach. Compare Intel Labs’ result with the #1 entry on the list from NNSA and IBM Research running on BlueGeneQ. For the same graph size (2^32 vertices, over 4 billion), that team delivered 4.4x higher performance – but also using more than 10 times the compute nodes and 17 times the cores. Although some of this is due to architectural differences, much of the reason for Intel’s improved per-core efficiency was in the algorithmic optimizations from our researchers.

The team in Intel Labs is excited to be among the world-class researchers tackling this new challenge.

To make this vision a reality, the ISTC for Pervasive Computing brings a uniquely qualified team of academics from top US universities together with Intel researchers to conduct research and guide this nascent field. The center is co-led by Prof Dieter Fox from the University of Washington at Seattle and Intel Principal Engineer, Anthony LaMarca. The center participants include other UW faculty, and professors from several top-tier schools (Cornell, Georgia Tech, Rochester, Stanford, and UCLA). Together with their bright young students, these thought leaders have laid out an exciting bevy of applications-based research topics. These are organized into the following ISTC-PC themes: 

- Low Power Sensing and Communications: Enable continuous unobtrusive awareness of people for long periods of time by adapting a system-level approach to power management including energy harvesting from ambient sources. 

- Understanding Human State and Activities: Recognition of the context of a user’s interactions with other people, smart objects and sensors in the environment. And get this, all in real time. 

- Personalization and Adaptation: Continuous learning of user’s preferences and adapting to new activities. 

These technology themes are essential building blocks to enable the pervasive computing applications of the future. Great thing about this center is that realistic scenarios from everyday lives will be used to drive the research. More concretely, following are the 5 projects that the ISTC-PC researchers plan to focus on: 

1. Mobile Systems for Improved Health and Wellness: Most peoples’ lives have fairly predictable daily patterns and activities. This project aims to develop mobile systems that are able to learn the user’s routines and goals using a variety of sensing platforms. Using stress sensing modalities, it aims to help users manage stress in their lives, and improve their overall well-being. 

2. Learning and Labeling Family Routines: Modern living is adding new complexity around family coordination, scheduling of activities, and interaction amongst family members. This project aims to track and understand these routines. 

3. Pervasive Perceptual Activity Sensing Infrastructure: This project aims to develop human activity sensing infrastructure that is capable of perpetual operation, using power harvesting from ambient sources. 

4. Task Assistance and Learning in Smart Spaces: Are you stumped by the complex set of instructions with tens of small parts like in assembling a home office furniture set, or making a cheesecake? Wish there was a guide alongside watching and advising, and suggesting a solution if you are stuck. This project will create local task spaces capable of helping users with physical tasks, by combining the user’s context, gestures, and voice inputs, and helping them complete a multi-step project. 

5. Understanding Objects, Scenes and People in Activities: This project will research computer vision-based approaches to enable rich and robust recognition of objects, scenes, and human actions in the context of daily activities. 

One key aspect of this research funding from Intel is that it is open and truly collaborative and all IP will be dedicated to the public. The idea is to conduct research and foster an ecosystem that encourages new computing paradigms with new usages which have the potential to make a large societal impact. 

Who knows, in the not so distant future we may have homes with walls and countertops that just do the right thing – facilitate our cooking, help organize and coordinate family activities, or sense our bad day at the office and welcome us home with soothing music. I am really looking forward to the exciting new developments at the ISTC for Pervasive Computing.

As part of the ongoing commitment in supporting research at Universities, Intel has contributed over $1M to support top PhD students across the nation for 1 year of their research. The Intel PhD Fellowship Program is a very competitive process where students must first be pre-selected by their universities to be able to apply for the fellowship. Each selected student submits a thorough application which is reviewed by Intel Fellows and senior technologists who choose the winners. This is a very prestigious award, and winning students are all leaders in their field and come very highly recommended by their university and/or industry partners. 

The fellowship program was started in the early 90′s by Gordon Moore to recognize and honor top students for their leading edge research in areas that would benefit the mankind; it was open to all fields of research. Gordon wanted to give back to those universities and communities who excelled at producing the top students. It was a way to build long lasting relationships with these universities, the professors and help create the next generation of technology leaders. The program has been supported every year for nearly 2 decades. Today’s program keeps that focus and also places an emphasis on developing students who are well aware of issues facing the Semiconductor, High Tech/IT fields. Every winning student is assigned a technical mentor in Intel who is also a leader in their field. Students are encouraged to work through their mentor and develop a deep, understanding of the technical issues facing the industry and be on the forefront of solving the technical challenges that lie ahead. 

This year, 21 fellowships were awarded. All of the winning students were invited to Intel in Oregon for the PhD Fellowship Forum. During this forum, the students were able to meet and hear lectures from top technical leaders across the company including Limor Fix, Vida Ilderem, Mike Mayberry, Kelin Kuhn, and many others. They also attended a networking dinner with many of the speakers as well as other Intel Fellows and Senior Principal Engineers. Intel is very proud to announce the list of this year’s winners – Congratulations to each one of you!!! 

Check out this video for highlights of the event. 

Don’t get me wrong, commodity DRAM processes are amazing feats of modern technology. DRAM process technologies incorporate the ability to hold massive memory capacity within a tiny piece of silicon all at an amazingly low manufacturing cost. However, with this exceptional memory density and cost structure brings limits on logic density and I/O performance; an area in which logic process technology optimized for a CPU really shines. We knew that future high-speed memory will need to conquer a challenging set of tradeoffs and achieve low cost and power as well as high density and speed. We came to the conclusion that mating DRAM and a logic process based I/O buffer using 3D stacking could be the way to solve the dilemma. We found out that once we placed a multi-layer DRAM stack on top of a logic layer, we could solve another memory problem which limits the ability to efficiently transfer data from the DRAM memory cells to the corresponding I/O circuits.

Getting the data out of the memory cells to the I/O is analogous to the difficulty of navigating the streets of a crowded city. However, placing the logic layer underneath the DRAM stack has a similar effect to building a high-speed subway system underneath the streets, bypassing encumbrances such as the DRAM process as well as the routing restricted memory arrays. Additionally, the adjacent logic layer enables integration of an intelligent control logic to hide the complexities of the DRAM array access, allowing the microprocessor memory controller to employ much more straightforward access protocols than what has been achievable in the past.

The result of this joint research project between Micron Technology and Intel has been the development of some key achievements. Last year, Intel designed and demonstrated an I/O prototype that achieved a record-breaking 1.4 milliwatts per gigabit per second energy efficiency that was optimized for this hybrid-stacked DRAM application. The two companies worked together to jointly develop and specify a high-bandwidth memory architecture and protocol for a prototype that was designed and manufactured this year by Micron. This hybrid-stacked DRAM prototype, known as the Hybrid Memory Cube (HMC), is the world’s highest bandwidth DRAM device with sustained transfer rates of 1 terabit per second (trillion bits per second). On top of that, it is also the most energy efficient DRAM ever built when measured in number of bits transferred versus energy consumed. This groundbreaking prototype has 10 times the bandwidth and 7 times the energy efficiency than even the most advanced DDR3 memory module available.

These developments will likely have a fundamental impact on data centers and supercomputers that thirst for low-power high-bandwidth memory accesses. With this technology, next generation systems formerly limited by memory performance will be able to scale dramatically while maintaining strict power and form factor budgets. Additionally, these developments may play a key role in the optimization of system architectures and memory hierarchies of future mainstream systems in the client and server markets.

The purpose of this chip is to advance near-threshold voltage (NTV) computing and to demonstrate the energy benefits of NTV designs, which promise better energy efficiency. Most digital designs operate at nominal voltages – about 1V today. NTV circuits operate around 400-500 millivolts – very close to the “threshold” voltage at which transistors turn on and begin to conduct current. It is challenging to run electronics reliably at such reduced voltages. To put it simply, the difference between a “1″ and a “0″ in terms of electrical signal levels become very small, so a variety of noise sources can cause logic levels to be misread, leading to functional failures. The benefit, however, is that energy consumption reaches an absolute minimum in the NTV regime with a sizeable ~5-10X improvement over nominal operation. The key challenge is to lock-in this excellent energy efficiency benefit at NTV while mitigating performance loss.

Several years of research went into realizing our first NTV IA Processor. Extreme sensitivity to power supply and transistor threshold voltage variations complicates NTV design. We had to develop NTV-aware techniques to improve design robustness for reliable operation. We re-designed the on-die caches and logic and incorporated new circuit design techniques and methods to tolerate variations at NTV, while increasing the chip’s dynamic operational range. For this test case, we picked one of our crown jewels – our first super-scalar Pentium core, though the same techniques could be applied to any Intel digital designs in the future.

The result is a “heat-sink free” processor core that can be placed in NTV mode at <10mW with minimum-energy and 5X better energy efficiency. The processor also provides wide dynamic operational range and can run at higher frequencies (~10X) when performance is needed. The new “always-on” – yet “ultra low power state” can keep applications running and is ideal whenever compute demands are modest. While this prototype may not become a product itself, conclusions from the NTV research could lead to the integration of scalable NTV technology across a wide range of future products from mobile to HPC.

NTV technology isn’t just unique to processors. The concepts are promising to a wide range of digital platforms and opens up many new “use conditions”, taking “always on” to a new level. For instance, this could be compelling for smart phones, tablets and other devices allowing “one” design to efficiently scale all the way, obviating the need for heterogeneous architectures. Also, these ultra-low power levels could allow Intel architecture to expand into broader applications like embedded devices, which would include “everyday” devices such as home appliances and automobiles.

In fact, one goal of NTV research is to enable “zero power” architectures where power consumption is so low that we could power entire digital devices off solar energy, or off of the energy that surrounds us every day in the form of vibrations and ambient wireless signals. This gives us unfettered freedom so we can just leave our power cord and chargers behind. NTV research is particularly applicable to self-powered autonomous sensor networks and monitors strewn about our environment allowing computers to “see” and intelligently “react” to the world around us.

Finally, Justin’s keynote highlighted that NTV research is quickly maturing and the processor is a key enabler for Extreme Scale Computing. Extreme scale means getting the most energy-efficient performance for the power spent – achieving 1000x performance at only 10x the power, or perhaps 10x performance at 1/10 the power. This could help us realize massive Exa-scale supercomputers or put trillions of computations per second in our pockets, while being environmentally-aware.

Way!

If applications were like road traffic, then web browsers used to be the country roads: Capable of handling some traffic at slow speeds but too underdeveloped to take a heavy load. This no longer is the case. Browser vendors have invested into their browser’s execution engines, increasing the speed limit on their country roads significantly. Still, native applications have a performance advantage.

This advantage is no longer just due to slower execution speeds. If you look at modern processors, they all come with some form of vector extensions that allow the processor to execute multiple operations at the same time. Keeping with the road analogy, native applications run on multi lane highways. Intel’s 2nd generation Core series just introduced AVX, which doubled the number of lanes compared to previous processor generations. Another performance boost available to native applications is the use of multiple roads: Most modern systems feature a multi-core processor.

Web applications so far have lost out in both regards. JavaScript, the language behind the web, does not give applications access to multiple cores, let alone vector instructions. Thus forcing me to use native applications where performance matters although I would prefer staying in the browser. Clearly, it is time for JavaScript to catch up.

This is where Parallel Extensions for JavaScript, code named River Trail, an Intel Labs project I am working on that is currently shown at IDF, comes into the game. River Trail brings the processing power of Intel’s multi-core CPUs and their vector extensions to web applications. With River Trail it will finally be possible to stay in the browser even for more compute intensive applications like photo editing.

What really excites me about the technology behind River Trail is its seamless integration with existing web technologies. River Trail extends JavaScript with a simple, yet powerful data-parallel programming model. Much effort was spent to make this extension feel as natural as possible. Our goal was to make writing web applications with River Trail as easy as writing regular JavaScript. Furthermore, as River Trail is embedded into JavaScript, it combines well with other upcoming HTML5 APIs. We in particular made sure that River Trail plays nicely with WebGL, a recently introduced JavaScript API to OpenGL used for 3D visualization in the browser: One of our demo applications is a physics simulation with more than 4000 bodies, where the computation is done using River Trail and visualization is performed with WebGL.

Bringing new technologies to the web immediately raises the question of their impact on the user’s safety. This is true for River Trail, as well. The web browser, by its nature, is on the front line of attack. JavaScript code, whether extended by River Trail or not, is loaded from remote systems that are outside of the user’s control and is executed on the local machine. Protecting the user from abuse and ensuring the security of River Trail therefore were major concerns in the design. River Trail was designed to inherit the security traits of JavaScript and I am confident to say that our extensions to JavaScript do not add any further attack surface to the browser.

Will River Trail be the end to native applications? Probably not. Will it lead to improved web applications and new kinds of usages for the web browser? Hopefully so! River Trail is available todayas an add-on to the Firefox web browser. You are invited to join us and refine it, make use of it, change the web. We have built a computing high-way for the web browser. Let’s make use of it.

We would like to utilize Intel Developer Forum (IDF) as an opportunity to introduce to you the latest advancements in our 3D web project and please do stop by Intel Labs Pavilion to interact with the 3D web.

For the 3D Web, the first task is to define a method how to “code” 3D scenes. Here, the IVCI approach is a declarative one – our XML3D language describes all components of the scene, including the 3D objects, their positions and transformations, textures and surface properties, shaders, lights and cameras. XML3D is based on XML and fits very nicely into HMTL5 – all the scene components become parts of the HTML domain object model, exactly like text, 2D graphics and videos today. And, all the established ways of “Web programming” naturally extend to the 3D scenes – it is, for instance, extremely simple to change the position of a 3D object from Javascript, and flying that spaceship along a trajectory is straightforward. And, the color and surface properties can be changed via CSS, with zero programming effort involved.

Procedural approaches like WebGL do require deep knowledge of graphics programming (like OpenGL) that is not normally available with Web content developers and programmers. XML3D does not require any new (to a Web developer) programming skills – only knowledge of content creation tools that help to create the scene description.

On the client side, the IVCI team has produced extensions to the Firefox and Chromium browsers that parse the XML3D language and render the 3D scenes in a browser window. The beauty of a scene description (rather than an OpenGL program) is that the browser can select the right rendering method for any given device, and the same scene description will look best on a wide range of devices. Our prototype browser extensions support a highest quality ray tracing renderer, WebGL and OpenGL ES.

At IDF, we are showing end to end demos of a 3D shopping experience, a virtual museum and a car configurator. You can find us in the Intel Labs pavilion, booth 5080 in the exhibition hall.

Complete information about the 3D Web project can be found on http://www.xml3d.org.

Looking at the next generation of wireless technologies, here at Intel, we are searching for disruptive methods to add network capacity with a focus on greater efficiency in multimedia content delivery that enhances user experience. Amongst the key technologies under research are: 1) optimized compression of video content to reduce network traffic, 2) intelligent aggregation of capacity across multiple radio networks, and 3) video quality aware optimization for wireless network.

At the 2011 Fall IDF, we are showing a demo [Scalable Video Over Multi-Radio Networks] that illustrates the gains possible by combining these technologies. We employ optimized video compression with Scalable Video Coding (H.264 SVC) to establish different resolutions: a base layer, which provides a baseline level of video QoE; and one or more enhancement layers that build upon the base layer with increasing levels of quality of experience (QoE) – in any combination of temporal, spatial, or picture quality dimensions.

We then show how content delivery is judiciously balanced over different radio networks (cellular and WiFi). While the base layer is continuously transmitted over cellular, the enhancement layers are opportunistically delivered when available capacity is present at WiFi hotspots, providing the user with better quality of video. Figure below illustrates this concept. The advantage for service providers is that this offers a way to balance load across different kinds of spectrum – licensed/unlicensed, WAN/LAN, etc. For users, the benefit is a flexible, or scalable QoE based on their local access to different spectrum bands.

As additional eye-candy we included several post processing special effects (thanks to Ben Segovia). Just to clarify: those are not specific to ray tracing and have been seen in some games already. They are operating on the pixels of the rendered image (not on the 3D scene) – in our case directly on the Knights Ferry card. They can improve the perception of the rendered scene dramatically.

• Depth of Field: The effect is well known to photographers. If we want the spectator to focus on a certain area in the picture then the less relevant parts can be blurred. Therefore the object of interest is still sharp and will attract the main attention.
     

   

  Depth of field on/off (3% performance difference) 

• HDR Bloom: If in reality we leave from a dark room into the bright outside our eyes are adjusting over a few seconds to the new brightness. The same can also be observed with digital (video) cameras that mimic this behavior and adjust the brightness spectrum to a pleasantly looking image. While doing this cameras might produce a bloom that can also “bleed” into other objects.
     

   

  Overbright scene with HDR on/off (2% performance difference) 

   

  

   

  Bloom effect 

   

• Inter-lens reflections: While camera manufacturers are trying to avoid lens flares computer games and movies are often adding them as an artistic element. In this implementation several smaller sized version of the image, shifted to a specific color (e.g. green, blue and orange) will be blended into the original image.
•   Subtle (image-based) inter-lens reflections (0.1% performance difference)

Another step we are doing for the first time is a smart way of anti-aliasing (thanks to Ingo Wald and Ben Segovia). There are different possibilities on how to do anti-aliasing. Most of them work pretty much brute-force and therefore invest additional calculations in areas where the improvement might not be noticeable. Our implementation will be applied after the image has been rendered. As ray tracing easily allows to just shoot a few rays for refinement we are analyzing each pixel depending on two factors if it requires more anti-aliasing:

• The angle of the polygon that got hit at that pixel
• The polygon mesh ID of that object

If there is a high enough variation in the angle or a different mesh ID is found we will shoot 16 more rays (supersampling) for that specific pixel and average the resulting color into that pixel. (Please note that the difference can be seen best in the full-sized images that appear after clicking the thumbnails.)

Courtyard view: Smart Anti-Aliasing off

Courtyard view: Smart Anti-Aliasing on (59% performance difference)

Close-up on cable: Smart Anti-Aliasing off

Close-up on cable: Smart Anti-Aliasing on (32% performance difference)

For future implementations more criteria like the color of the pixel (e.g. imagine an almost black spot in the picture – aliasing will not be noticeable here) or the color between neighboring pixels could be added. Further before comparing those colors MLAA could be used to reduce aliasing first and then later only certain areas could be refined through shooting new rays. Tweaking the numbers of additional rays to 4 or 8 might lead to better performance/quality tradeoffs.

We would be happy to show you the real-time demo at IDF at the Intel Labs pavilion, booth 5080 in the exhibition hall.

Additional thanks to Ram Nalla, Nathaniel Hitchborn, Sven Woop, Alexey Soupikov, Alexander Reshetov.

The system that can hold the eight double-sized PCI-Express cards has been provided by Colfax International to us. Thanks!