Research@Intel

ISADS: Using images to detect melanoma

2008-08-22T18:10:04Z

Researchers from the Intel lab in Pittsburgh have been working with physicians on a tool to assist them in diagnosing skin cancer. At IDF in San Francisco this week, they demonstrated the project. Once a digital photo of the skin lesion is captured, doctors can use the image to query for similar cases in a large database of skin lesions that have already been diagnosed. Having access to this collection of relevant knowledge, doctors will have more information to treat their patients.

ISADS stands for Interactive Search Assisted Decision Support. The goal is to enable doctors to make more informed decisions about a given case by presenting relevant annotated cases from large medical repositories. Unlike systems that make decisions for the physicians, ISADS is a tool for search and comparison to medically relevant annotated medical images, where retrieval is based on image content rather than text or metadata.

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Researcher Mei Chen describes the project: One application we are working on is ISADS for melanoma detection. Melanoma is the most fatal kind of skin cancer, and its incidence has been increasing in the U.S. To develop an application for real clinical practice, we collaborate with physicians from University of Pittsburgh http://www.upmc.com/home.htm to make it fit into the clinical work flow. To achieve this we streamline and automate the operations as well as designing the interface to be physician-friendly with just the right features.

Automated interpretation of medical images is challenging. From removing artifacts to finding lesion boundaries to extracting color characteristics, we develop algorithms that are driven by domain-knowledge, employ computer vision techniques and statistical machine learning to keep improving the performance. Hopefully in time, this tool will enable doctors to more quickly and accurately diagnose melanoma.

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Wireless Power & "Sensitive" Robots: videos from IDF

2008-08-21T17:00:58Z

Justin Rattner gave a pretty fascinating keynote at IDF today about what he thought the big advances would be by 2050. He included three demonstrations from some out-there research that is happening in some of intel’s “Lab-lets” in Seattle and Pittsburgh. I had a chance to chat with a few of the researchers a few weeks before to get a sneak peak and grabbed some video of their work - take a look at the videos below to see what Rattner showed today in his keynote:

Cutting last cord - power:

Imagine having the ability to walk into an airport or room with your laptop and instead of consuming battery, it is recharged. Based on principles proposed by MIT physicists, Intel researchers have been working on a Wireless Resonant Energy Link (WREL). Rattner demonstrated powering a 60-watt light bulb without the use of a plug or wire of any kind, which is more than is needed for a typical laptop. Josh Smith, a principle engineer at Intel, and intern Alanson Sample are leading the research effort out of our Seattle lab and I had a chance to see it in action and chat with him before the keynote - check out the video to see for yourself:

“Sensitive” Robots:

Rattner demonstrated two working personal robot prototypes developed at Intel’s research labs - these are meant to someday be at home with you instead of in a manufacturing floor. One of the demonstrations showed electric field pre-touch that has been built into a robot hand. The technique is a novel sense used by fish but not humans, so it can “feel” objects before it even touches them. The other demonstration was a complete autonomous mobile manipulation robot that can recognize faces and interpret and execute commands as generic as “please clean this mess” using state-of-the-art motion planning, manipulation, perception and artificial intelligence. Check out this video I took just before the keynote started

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Connected Visual Computing: The Next Level in Human-computer Interaction by Inga Vailionis

2008-08-18T16:51:38Z

Today at an intel developer forum press briefing, Intel Fellow Jim Held provided us with some insights into CVC, or Connected Visual Computing. He discussed what projects and technologies researchers at Intel are working on for enabling it.

To me, CVC is primarily about the next level in human-computer interaction. It is about fascinating new ways people can interact with computers - and each other. In the not so distant past, the Internet to me meant going to the static HTML pages and patiently waiting for them to load. Then, clicking on links and scrolling through the pages, all alone in my room.

CVC has been changing that dramatically. Already today, I can go to virtual computer-simulated 3D spaces to learn, play PC games, or simply hang out with my friends. Some choices are already here, such as Google Earth, virtual worlds, or augmented reality navigation devices. These are just the first and relatively primitive examples of the big things to come.

But forget about me. The true CVC trendsetters today are 4-11 old kids. They make up over half of all virtual world users. Today, virtual worlds provide playgrounds and meeting places for over a hundred million of kids.

Why do kids go there?

They want to play games together, chat — or buy virtual pets. These kids will grow up accustomed to interacting in immersive, computer-simulated 3D spaces, which will become a part of their private and business lives.

Intel needs to make sure that its platforms are relevant to these kids in 10-15 years. Challenges abound: from designing many core processors to developing better graphics and parallel software. But they have to be resolved to make sure, that Intel platforms are capable of running the immersive 3D applications of the future.

Inga Vailionis is a technology manager in intel’s microprocessor technology labs focused on connected visual computing

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How to Count Cores

2008-08-11T17:13:08Z

One of the most abused terms today is “core count”. Depending on who you ask, a core might mean a full-fledged IA Core (e.g. a Core 2), or it might mean something substantially less…like a small processing element with an ALU and local storage. Recently, I was guilty of this, too. In my defense, I was taking a decidedly software-oriented view of core count: what is the overall degree of parallelism have to find in my application?

At Intel, we would probably define a core as having the rough functionality of a CPU core (including one core of these).

For my purposes, I had a slightly different definition in mind. I define this essentially as the SIMD ISA width (or effective SIMD width if the micro-architecture has implicit constraints, like branch coherence) times the per core (HW) thread count times the core count. (Note that I might further multiplex multiple lightweight software threads on each hardware thread to tolerate memory system latencies, but we’ll leave that out…for now.) So, consider the Core2Duo processors: Each core has 1 thread per core, 4-wide (32-bit) SIMD ISA and there are 2 cores. The out-of-order logic will take care of the latency hiding for me. So, to fully utilize the these cores, I’m going to want to find 1x2x4 = 8-way parallelism. On a dual socket system, double this to 16-way. Upgrade to quad core, and we’re talking about 32-way. Go crazy and move to a quad socket system and we’re at 64-way! Now consider quadrupling both the per-core SIMD width to 16 and the number of hardware threads per core to 4.

I suppose it used to be that I’d think in terms of a few threads running some apps that had SIMD parallelism. For some apps this still works, using different types of parallelism expression (like wrapping parallel loops around vectorizable inner loops)…consider an image processing algorithm like frequency coding for compression that operates on small sub-blocks of the image or video frame. However, to get at the maximal scalability, I generally want to think in terms of the parallelism as a whole. Even in the video processing scenario, I’ll want to start considering the parallelism across the width, height, and timestamp of the frame. This is probably a better way to think when architecting for very scalable applications. In essence, think about all the parallelism exposed to the software layers.

Of course, there are other issues: explicit vector instructions (e.g. SSE) have some benefits in terms of atomicity guarantees of the vector instructions; the ability to perform scalar operations in parallel issue slots to the vector instuctrions; and the latency hiding benefits of software multi-“thread”ing is significantly impacted by how the cores access memory and how the caches work (e.g., whether they exist at all in the architecture). And so on.

I think it was relatively benign to use “core count” in this situation…however, from what I see reported on ours and our competitors’ product roadmaps, it can get a little confusing.

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Less is More: Increasing the Dynamic Operating Range of Intel Processors and Chipsets

2008-07-31T16:09:16Z

Voltage and power reductions in our products come from a broad engagement between process, design and architecture. For our latest 45nm products, the careful design of the SRAM cell and our invention of high-k metal gate transistors were key contributors to reducing minimum voltages. Previously, I wrote about the Climate Savers Computing Initiative and our research to achieve efficiency gains at the platform level.

Beyond energy efficient design lays the notion of powering our processors and chipsets over a much wider range of voltages. Let me share with you some important research we have underway that may lead to dramatic improvements in the dynamic operating range of our products.

Ever wonder why we don’t keep lowering the operating voltage for a processor or chipset in order to reduce power? As new markets, our customers, and end users demand low-power processors, every possibility is fair game, right? Unfortunately, manufacturing variations cause memory cells to become unreliable at low voltages. In a large memory structure, such as a cache or a register file, a small number of these cells require relatively higher voltages to function correctly. The minimum voltage at which the entire chip can reliably operate is referred to as Vcc-min. A small number of memory cells typically limit Vcc-min and, consequently, limit the operating range of our products.

Since reducing the supply voltage has a quadratic effect on the power consumed by the microprocessor, Vcc-min is a critical design parameter where low power operation is the goal. Reducing Vcc-min and enabling products to operate with lower supply voltages will allow each of our designs to address market segments where ultra-low power operation is an asset. In this manner we enable a much wider dynamic voltage range for our products. A wider dynamic voltage range makes our platforms more adaptive, with the ability to deliver maximum performance at high voltage when needed or the best MIPS/watt at low voltages when the platform is at or near idle.

In our circuit and microarchitecture labs, researchers are working on techniques that allow our designs to reliably operate at much lower voltages than they do today. Our microarchitecture lab is focusing on an architectural approach to the Vcc-min problem. The goal of this work is to develop adaptive memory structures that maximize performance when performance is most important (high voltages) while still enabling low voltage operation at a small performance loss when energy efficiency is most important. A good example of this approach is the versatile smart cache which incorporates a feature that we proposed recently at the International Symposium on Computer Architecture called “word-disable.”

The versatile smart cache is constructed with standard memory cells (SRAM or register file), a small number of which will fail at low voltages. To enable low voltage cache operation, word-disable identifies the words in the cache that contain these failing memory cells and then disables and excludes these sections from use. Since the versatile smart cache is constructed with standard memory cells and the entire cache is available for use, word-disable has minimal overhead when operating at high voltages. Word-disable causes a small performance penalty during low voltage operation due to the loss of cache capacity that results from disabling parts of the cache.

Our circuit research lab is approaching the Vcc-min problem from a different angle: making adjustments to the basic circuit cells to allow for minimization of Vcc-min (with minimal impact on basic cell size). To investigate this research, we designed, fabricated and took measurements from a 1.2V, 65nm video encoding motion estimation chip that we showcased at the International Solid-State Circuits Conference and at our Research at Intel Day event last month.

Ultra-low supply voltages would reduce the noise margins and reliability across process SKUs, especially affecting weak keeper devices, such as flip flops. One design improvement to avoid this issue is increasing the channel length of transistors in transmission gates and opportunistically increasing full-interrupted keepers. This, combined with only allowing single stage multiplexers with a maximum of two inputs, improves circuit robustness at ultra-low voltages.

Usage of lower supply voltage regions requires the use of voltage level shifters. Instead of using the standard single stage topology, a two-stage cascaded split-output level shifter was implemented. This topology enabled more robust low power operation, allowing reductions of 20% in total energy. Using more robust level shifters, sequentials and datapath logic, this research chip was able to achieve a very wide dynamic range. In testing, it exhibited a voltage range from 230mV to 1.4V. This translated into a dynamic power range from 14.4 microwatts (at 4.2MHz) to 82 milliwatts (at 2.4 GHz) – a factor of nearly 5700x!

With more and more customers asking for products with a wide dynamic range of operation, these techniques may prove vital to our future low-power and energy-efficient products.

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Rounding up Research Day

2008-07-20T23:20:27Z

Now that the dust has settled from the 6th Annual Research At Intel Day press event, I am still amazed at the breadth and variety of research projects that were on display. Researchers from Israel, China, Russia and the US brought their ideas to the Computer History Museum on June 11. The contrast between the historic computing artifacts and the possible future of technology was really inspiring.

Demos ranged from technology for long term healthcare to object recognition. There were mood phones and environmental smog detectors; the latest advances with the Classmate PC to hardware assisted malware detection. Check out these videos to learn more about some of the projects shown at Research Day.

Ultra-low Video Encoding Accelerator

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Emerging Markets - Design For The Middle Class

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Real-Time Visual Mobile Object Recognition

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Technology For Long-Term Care

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Mobile Heart Health “The Mood Phone”

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Unwelcome Advice

2008-06-30T19:11:00Z

Generally speaking, you don’t want to deliver any kind of difficult news to customers, partners, etc. Some of us are lucky enough to talk to folks about the performance and capabilities of our processors, shipping and soon-to-ship. Some of us, however, face a somewhat more challenging situation: explaining how to tap into this performance. I find myself in this situation often, as I frequently talk to external developers about our ongoing research in programming for multi-core and terascale. The discussion typically goes in one of two directions (the relative distribution has changed over time).

Sometimes, the developers are trying to do the minimal amount of work they need to do to tap dual- and quad-core performance…and perhaps stretch this to our DP and MP (dual and quad socket…or up to 16 cores) systems. I suppose this was the branch most discussions took a couple of years ago.
Increasingly, we are discussing how to scale performance to core counts that we aren’t yet shipping (but in some cases we’ve hinted heavily that we’re heading in this direction). Dozens, hundreds, and even thousands of cores are not unusual design points around which the conversations meander. Over time, I find that developers migrate their thinking from the first kind of discussion to the second.

We have starkly different conversations about these two paths. For the incremental path, the performance bar is often much lower and the tools that programmers want support a more incremental adoption path. We tend to discuss how to use new tools with old tools, support legacy code that (in some cases) is scarcely supported internally by the developers themselves, and so on. The second path usually requires at least some degree of going back to the algorithmic drawing board and rethinking some of the core methods they implement. This also presents the “opportunity” for a major refactoring of their code base, including changes in languages, libraries, and engineering methodologies and conventions they’ve adhered to for (often) most of the their software’s existence.

Ultimately, the advice I’ll offer is that these developers should start thinking about tens, hundreds, and thousands of cores now in their algorithmic development and deployment pipeline. This starts at a pretty early stage of development; usually, the basic logic of the application should be influenced because it drives the asymptotic parallelism behaviors. Consider a common pattern of optimization we’ve seen in single core tuning: the use of locally adaptive algorithms to heuristically reduce the computation time. By definition, this introduces dependences in the computation that are beneficial in the single core case but limit parallelism for multi-core. Similar choices are made about libraries and programming languages that optimize for single core performance (or even small-way parallelism), but sacrifice long-term scalability.

Eventually, developers realize that the end point is on the other side of a mountain of silicon innovations, but there are two routes: a flat, but potentially longer and more circuitous route around the issues that arise with increased parallelism; and a direct route that the developer largely pays for earlier. Front-loading at least some of this transition is often less costly in the long run and positions them to more competitively reap the benefits of our silicon innovations over time. It’s not quite as simple as this binary choice, but you get the basic idea…program for as many cores as possible, even if it is more cores than are currently in shipping products.

Folks from traditional or emerging HPC vertical either know this (and have known it for many years) or come to this conclusion pretty quickly (*). For more mainstream application developers, this advice is usually unwelcome…but it is an encouraging sign that developers are increasingly coming to this realization on their own.

[Note: Some follow up here.]

(*) However, HPC developers have the interesting problem of (depending on how you look at it) scaling down a “plane” of parallelism or scaling up an inner level of parallelism to map efficiently on to multi-core silicon in their clusters/data centers/grids…which has sometimes subtle differences from the single, dual and quad-core based clusters they’ve been used to programming.

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Preventing Identity fraud with Secure Digital Wallets by Prashant Dewan

2008-06-16T15:30:05Z

Intel’s Secure Digital Wallet (SDW) research enables the users to manage their credentials for various banks, e-commerce websites, e-mail servers on Intel laptops, desktops and MIDs so that their susceptibility to identity fraud is minimized. Identity fraud is one of the ways by which the criminals on the Internet steal innocent user’s credentials and use it for illegitimate purposes. Criminals can steal credit card numbers to buy things on the Internet and tarnish our credit history. It can take a few days to a few months with lots of pain for the owner of the card to recover from such misuse. In the extreme cases the damage done could be irreparable.

SDW is based on security visor developed using Intel® VT technology to restrict illegitimate accesses to user credentials in transit and at rest. The access control is enforced under the operating system without modifying the OS kernel. More specifically the confidential information is encrypted while on disk and maintained in an enclave while in memory in a fashion that only an authenticated and validated code can access this information. Even the graphics rendered on the screen is under strict access control enforced by the security visor.

For the end users, SDW will increase their confidence in online transactions since it will block traditional malware like key loggers, screen scrapers, hardware keyboard sniffers. It will significantly reduce phishing attacks without forcing the user to look at difficult to read digital certificates. Today one of the peeve points of end-users is the multitude of websites and remembering their login and passwords. SDW will alleviate that pain and will remember the user’s login/passwords thereby making online transactions a more pleasant and safer experience.

The fraud costs are borne by the merchants or the credit card companies in many countries. The solutions out there today need either the merchants and/or the card companies to modify their infrastructure thereby adding to their cost. Moreover, since the adoption rates are generally slow, companies find it hard to justify the cost. SDW will not need any changes on the bank’s/merchant’s infrastructure and will work on a large number of Intel platforms already in the market. As a result merchants will see a significant reduction in risk and money spent on chargebacks.

Today, SDW is a research project. As we mature the technology, hopefully we will see it available one day.

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Prashant Dewan is a security researcher in CTG. His research interests are network and platform security, virtualization and decentralized networks. He has a PhD in computer science and has been working at Intel since 2004.

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Applications can be protected against runtime attacks! by Ravi Sahita

2008-06-13T22:00:23Z

We have seen regular reports from security vendors of malware becoming increasingly stealthier and polymorphic. Most countermeasures have focused in the area of reactive approaches such as anti-virus scanning, which doesn’t help much here. Intrusion prevention systems help, but are susceptible to attacks themselves – this is a problem since the protection and the attacks are operating in a level playing field! We have been analyzing these types of attacks in our lab and have approached the mitigation of this problem from a different view of protecting the applications in-place such that malware may still execute but will not have any negative impact on the security of the application. What we mean by in-place, is that the applications do not have to change their programming model or use of OS services, instead the program is protected in the environment within which it executes. Given these advanced attacks, in-place protection is important to today’s critical applications!

Our approach has been to protect the program at a fundamental level and from a higher privilege to ensure separation between the protected piece and the protector. To that end, we have been using our virtualization extensions (Intel® VT) to build a research prototype security visor. VT provides the necessary hardware hooks to virtualize OS page tables – using this, we have designed a page table partitioning algorithm to protect program memory such that the program cannot be tampered with, any dynamic data it allocates is accessible only to the program and any API attacks into the program can be prevented. Our protection scheme is driven by software measurement schemes we have described earlier in a paper published in the Technology@Intel magazine. Our page table partitioning approach is called VT Integrity Services and is described in more detail here, and we would love to hear your feedback on this approach.

The runtime protection for the application is important not just from the correct local execution of the application but also to be able to subsequently perform remote attestation of the protected application. This approach has applications to many usages. Intel® TXT provides us with the necessary secure storage and reporting mechanisms to ensure that the security visor we load, is the correct (read trusted) one. Additionally, the hardware platform can enforce that virtualization mode is turned on only when it is used via TXT – which enforces that the security visor should be a signed piece of code. What we are demonstrating at the current Research @ Intel day is the on-demand protection of an application – this is an avenue we have been investigating to be able to use this approach on power-sensitive devices like ultra-mobile devices. We are demonstrating that the on-demand trusted launch of the security visor can be used to protect the application only when required, so that the power usage due to running the Security Visor can be minimized to the application lifetime. Hope to hear your feedback on our research.

Ravi Sahita is a Senior Researcher in the Communication Technology Lab in Intel’s Corporate Technology Group. Ravi is currently working on platform approaches to address computer security issues. Ravi has contributed to Intel® AMT, Intel® NetStructure® products and the open sourced Intel® Common Open Policy Services (COPS) client SDK. Ravi is a contributing member of the Internet Engineering Task Force (IETF) and the Trusted Computing Group (TCG) standards bodies. He received his B.E. in Computer Engineering from the University of Bombay, and an M.S. in Computer Science from Iowa State University.

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Interactive 3D Streaming by Alexander Sterkin

2008-06-12T00:30:00Z

Second Life® and World of Warcraft® are among the most prominent MMOGs. They demand lots of computing power – both from the CPU and Graphics. These demands overload any mobile device of today or near future, even including MIDs. By the time the mobile clients have caught up, the performance requirements for MMOGs will grow higher yet.

The 3D Streaming technology developed by Comverse® and Intel computes and renders the MMOG content on a powerful backend server, then smartly compresses and streams the graphics onto a client. A network gateway designed by Comverse allows streaming over both WiMAX and 3G cellular networks. With advanced software optimizations including SSE usage, a single Xeon 5400 backend system can serve simultaneously up to 14 clients.

What does this mean for users of Intel platforms? In fact, the Comverse 3D Streaming capability offers a great user experience across all Intel platforms. On the backend, it’s the opportunity to offer the power of visual computing on high-end IA multicore platforms. On the client, it’s a chance to drive the demand for MIDs over non-IA smartphones by offering content better suited for larger screens and more sophisticated UI offered by MIDs. Overall, it’s a chance for telecom operators and content providers to offer a completely new service – running on the infrastructure that’s optimized for IA end-to-end.

Alexander Sterkin, Sr. SW Application Engineer in Intel’s Software & Solutions Group is based in Israel. The main focus of his work is providing technical training, consultation, and hands-on assistance to SW developers in areas of architecturing, technologies, support and influence of leading ISVs helping them deliver to the market product optimized for IA. Alexander holds Ph.D. degree from Weizmann Institute (Israel) in the field of Brain Research.

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Research Takes a Flying Leap into the Future

2008-05-31T16:45:34Z

Ever wonder where ideas for technologies like USB, 802.11n, PCI, or Serial ATA come from? Or maybe you’ve heard of the free application MashMaker that lets you create your own version of Web pages combining the information you want from multiple sites into one, putting it all together at once on your computer screen. Many of them had their genesis in Intel’s R&D labs.

We often have our own “science fairs” at Intel, for sharing research internally with product groups. But once a year we open our doors to media, giving the public a glimpse into Intel and the potential for technology near and far-out future. That event is coming up on June 11th and we’ll be creating an online experience here at this blog and in the special press room site. There will be plenty of photos and videos to feel like you were there which will be updated in coming week and in real time on June 11th.

This year the event is at the Computer History Museum. It’s a pretty massive showing of more than 75 projects demonstrating the latest in technology innovation from researchers. After Justin Rattner (Intel’s CTO) welcomes everyone, the media will set set out to go find the “next big thing” among the demonstrations in areas such as: “green” technology, robotics, scientific discovery, healthcare, the latest in mobility and microprocessor innovation that continues to push the innovation envelope.

We have a few passes for bloggers in the Bay Area, so if you are a blogger reading this, please let me know if you are interested in the comment section by June 9, and I’ll follow up with you. Tom Foremski of SiliconValleyWatcher , Hubert Nguyen of Ubergizmo and others are planning to be there.

This video gives a taste for how Intel boldly approaches research and how projects actually play a vital role in the future success of next generation computer chips and the industry as a whole with standards.

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Intel CTO predicts physical computers will eventually disappear into walls, cars and homes in Intel’s next 40 years

2008-05-19T19:02:30Z

I had a chance to chat with Justin Rattner, Intel CTO, as he reflected on Intel’s first 40 years and looked ahead to the next 40 years. He says instead of technology being an evolution over time, big revolutionary changes tend to happen in rapid “giant leaps”. He thinks the next major leap will be in the human interface with technology, with potential future breakthroughs in processing that would have the physical boxes of computers disappear into the fabric of our daily lives. Watch this video to hear Justin describe it himself:

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Madeleine Glick on Polymer waveguides for high speed board-level optical interconnects

2008-05-05T16:00:44Z

The continued growth of data rates in servers, routers and high-bandwidth computing systems has led to an increased interest in optical backplanes for these applications. Data rates in the backplane are increasing to several Gbps/channel and higher. The trend to multi-core and many core processors is an additional factor contributing to increasing bandwidth demands. Electrical interconnects pose serious challenges at bit rates at 10’s of Gb/s, optical links can alleviate many of these difficulties by improving bandwidth-length products and eliminating electromagnetic interference. There is a growing research effort to enable the move from the electrical to the optical domain.

View poster from recent lab open house event.

Polymers are seen as promising optical materials for transmission and even active devices because of their relative ease of manufacture and processing and potential cost effectiveness. At Intel and elsewhere in academia and industry researchers are investigating polymers for applications at both the chip and board levels. Compared to copper, optical technology has proven capabilities for ultra high data rate transmission, while compared to standard optical fiber, board level polymer waveguides offer the possibility of lower cost and a more compact technology that is compatible with electronic manufacturing technology. At the board level, to enable high data rate transfer over longer distances, the main research challenges are to achieve low optical losses in a robust, stable material and to develop low optical loss, low cost connectors to transfer the light to and from the polymer guides.

I have been working with the Centre for Photonic Systems at the University of Cambridge and Dow Corning to demonstrate the use of polymer waveguides at the board level in backplanes for high speed optical networks. My collaborators had previously developed novel polymer low loss devices that can be integrated with printed circuit boards. The siloxane polymers being used have been demonstrated to have low optical loss at data communications wavelengths (~0.04 dB/cm at 850 nm) and possess excellent mechanical and thermal properties compatible with lead-free solder reflow processes [ref 1,2]. The technology is now ready for research and demonstrations at the system level.

We are presenting a paper* at CLEO 2008 entitled “Terabit Capacity Passive Polymer Optical Backplane” which describes a novel, compact optical backplane featuring a scalable architecture using a planar array of multimode polymer waveguides. We have fabricated a proof of concept passive optical backplane enabling full non blocking communication between 10 cards (Fig. 1). The fabricated backplane is patterned from siloxane polymer by photolithographic techniques on a FR4 substrate, so it can also be used for mounting electronic components. The waveguide cross-section is 50 x 50 μm with a lateral separation of 250 μm to match conventional ribbon fiber and standard VCSEL and photodiode arrays. In this architecture we use bends for the 90° waveguide turns rather than corner reflectors to simplify the fabrication process. This also ensures that all crossings occur at 90° minimizing loss and crosstalk. The bend radius is 8 mm which, according to previous measurements, should induce additional loss of approximately 1 dB for a multimode fiber (MMF) input, while crossing losses are approximately 0.01 dB/crossing [ ref 3]. The low intrinsic waveguide loss together with the low crossing loss and low crosstalk values imply that this architecture has considerable scaling possibilities.

Full line-rate Gigabit Ethernet data transmission between a pair of computers was achieved over the backplane with no packet losses while using both the highest-loss link together with the corresponding link most susceptible to crosstalk. We also performed bit error rate measurements showing that each of the 100 on-board links can achieve error free transmission at 10 Gb/s indicating an aggregate interconnection capacity potential of a terabit per second. This is an exciting interdisciplinary research collaboration. Polymer waveguides have the advantage of being bit rate transparent and therefore scalable to higher data rates. We intend to examine various system architectures for data rate scaling including using multiple wavelengths to further increase the capacity. A high data rate backplane with a switchless architecture has the potential to lower the cost of the initial purchase of the blade server to incremental costs associated with purchasing additional cards.

Madeleine Glick is a principal research scientist at Intel Research Pittsburgh where she leads the optical systems work. Her research interests include signal processing and coding for optical links and optical switching for high performance computer interconnects. Madeleine has published over 100 articles. She is a Fellow of the Institute of Physics, a member of the UK EPSRC Peer Review College, an associate editor of the OSA Journal of Optical Networking and on the editorial advisory board of OSA Optics and Photonics News. She received a PhD in physics from Columbia University and is an adjunct professor in the ECE Department of Carnegie Mellon University.

Ref [1] J. D. Ingham, N. Bamiedakis, R. V. Penty, I. H. White, J. V. DeGroot Jr., T. V. Clapp, in Proc. CLEO 2006, [2] N. Bamiedakis et al. ICSO 2006 [3] N. Bamiedakis, J. Beals, R. V. Penty, I. H. White, J. V. DeGroot Jr., T. V. Clapp, in Proc. CLEO 2007

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Carry Small, Live Large

2008-04-09T07:01:00Z

One of the great computing revolutions of our time has been the dramatic reduction in size of processing components and the power they consume, making mobile computing a reality. The term mobile computer spans many types of devices, from laptop or notebook computers—now central to much of our work—to the smallest cell phones, which can not only provide a mundane telephone connection but also serve as an electronic organizer. The PDA, also originally part of this mobile revolution, has already largely been subsumed by the smart-phone market.

The key ingredients enabling this revolution are high-performance low-power processors, high-density memory, and standardized wireless communication. The latter isn’t a requirement for mobile computing per se but has become an essential ingredient of a computer’s everyday use; after all, a computer without a networking capability is no longer an interesting proposition.

Despite technical progress in designing and building true palm-sized computers, their use has tended to be limited in scope. Most people would probably agree that for any kind of serious computing task, certainly in the realm of enterprise applications, a notebook computer’s form factor is close to the bare minimum needed for effective HCI. We can conclude that one of the main barriers for effective work on a smart phone is the tiny display and keyboard and the poor user experience that results from the size-limited interaction. The form factor of a modern day laptop design has been honed over time, shaped by the design principle that form follows function. We might one day experience a revolution in GUI design, but I doubt this will radically change the baseline laptop’s size requirements. Many people have tried to improve the WIMP (windows, icons, menus, pointing devices) interface for many years with only minor success. As a result, for now, the best bet we have for improving the mobile computing experience is to augment the I/O peripherals to provide scaled-up interaction.

My Intel colleague Natalie Nielsen recently summed up this notion with the phrase “Carry Small, Live Large.” This embodies the idea that for mobility, small computers are attractive; they fit in a pocket and can be carried without encumbering their owner. “Live large” speaks to the idea that we have high expectations for our interactions with computers, and we expect them to positively impact our lives.

Carry Small

Since the early ’90s, I’ve been researching ways to overcome the limitations of small mobile computers, and I’ve helped build several prototypes that address different aspects of the problem. An idea for implementing the Carry Small, Live Large ideal became apparent to me after the first short-range wireless standards were realized in the late ’90s—a turning point for mobile computing. We no longer needed to interact with a mobile device directly; instead, much larger and more convenient nearby computers could provide the interface.

My research group’s Personal Server project embodied this concept[1]. Our goal was to extend the established paradigm of the personal computer and change how we think about using it. We aimed to design a personal server that you could carry in your pocket or purse and that you wouldn’t need to physically access. Instead, using wireless discovery and connection, you could interact with the server through another device across a wireless link.

Our initial prototypes used a client/server Web metaphor, and we based our first implementation on an XScale microprocessor running the Linux OS and a Web server. The device included enough solid state memory to store gigabytes worth of movies, music, photographs, and office documents—all accessible from a Web browser client running in the nearby computer infrastructure over an optimized wireless Bluetooth link.

Later, our Personal Server design was ported to a commercial cell phone based on the next-generation XScale processor. This gave users direct access to X-applications running on the device, all accessible using a Remote Frame Buffer protocol in communication with a remote client. The cell phone market continues to enjoy tremendous growth—selling over one billion units in 2006[2] —which shows the potential for a personal-server-integrated cell phone to impact mobile computing across the globe.

Remaining barriers

What barriers must we overcome for the Carry Small, Live Large model to flourish?

First, currently only a few smart-phone products can provide the computational resources that applications need for effective operation. The capabilities of inexpensive low-power mobile processors will certainly increase with time, so in the future we’re sure to see more cell phones with the potential to support enterprise-quality applications. Processing and memory capabilities continue to grow exponentially, so it won’t be long before the gap closes.

Second, there’s a lack of infrastructure. Any PC could in fact be a client to support this use model, but when users have access to a desktop PC, they should also be able to use the desktop for their actual work. The compelling new value proposition for a small mobile computer comes from the opportunity to serendipitously use displays and keyboards found nearby in unfamiliar locations.

Live large

An opportunity to solve this problem may result from the revolution we’re now seeing around large LCD displays—in part driven by the consumer electronics market and the digital home. Digital high-quality LCD displays are in a booming market as a result of attractive pricing and the FCC’s mandate that broadcast TV switch from analog to digital by 17 February 2009. So we’re likely to see a flurry of new TV purchases between now and then, which represents a market that all the big consumer electronics manufacturers will be keen to be part of. This will further drive down prices as the competition mounts. In fact, it has already resulted in considerable price reductions for large plasma and LCD TVs, now as low as one-fifth of the original introductory price.

These TVs come with built-in computing capabilities, and manufacturers will see the opportunity to use computation to differentiate their products. This year’s Consumer Electronics Show introduced flat-panel TVs with built-in Digital Media Adapters (DMAs) and the ability to connect to a network using Wi-Fi to access media stored on a home PC. With several companies actively making plans for digital movie download services to the home in the near future, the challenge will be how to enable a living-room TV—rather than the office or den PC—to show these movies. A DMA built into a TV can solve this problem while opening up a resource for mainstream use of the Carry Small, Live Large device interaction model. Once it’s available for the consumer electronics market, this technology, driven by the associated reduction in pricing, stands a good chance of becoming ubiquitous.

Going Urban

The applications for large high-quality displays aren’t limited to the home and are in fact widespread and equally applicable to the office and other shared spaces—in particular, urban public spaces. I’m continuously amazed by how many flat-panel screens are popping up around our towns and cities to display mundane information—restaurant menus, signs, corporate logos, transport schedules, and so forth. Even supermarkets are being fitted with multiple screens to display special offers as we walk through the aisles. Each of these venues has the potential to support a Carry Small, Live Large experience.

Urban computing today is mainly associated with direct interaction using the devices we carry and with the data that service-provider networks deliver. In the future, this could be a far richer experience, involving close coupling of the computation you carry with the displays and keyboards that you find around you.

Technology trends that will further support this use model are high-bandwidth short range radio, such as UltraWideBand, a standard now being introduced to support Wireless USB with speeds of up to 480 Mbps. At some point in the near future, we’ll cross a processing threshold, and our smart phones will be capable of running most of the high-end applications we’re interested in using. Furthermore, the short-range wireless bandwidth will be high enough for us to effectively connect to large wireless displays. At that point, urban computing will take on a whole new experience, and we’ll move closer to the pervasive computing vision, and the Carry Small, Live Large use model.

* * *

This blog originally appeared as Roy’s Editor-in-chief Introduction for IEEE Pervasive Computing, Issue 3, 2007.

If you would like to read more about this topic, or subscribe to the publication, please visit http://www.computer.org/pervasive

References

R. Want et al., “The Personal Server: Changing the Way We Think about Ubiquitous Computing,” Proc. Ubicomp 2002: 4th Int’l Conf. Ubiquitous Computing, LNCS 2498, Springer, 2002, pp. 194–209.
“Worldwide Mobile Phone 2007–2011 Forecast and Analysis,” IDC, May 2007; www.idc.com/getdoc.jsp?containerId=206583.

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Lester Memmott on Context Aware Computing

2008-04-08T19:54:22Z

Last week, the Intel Developer Forum (IDF) was held in Shanghai, China and one of the key messages was that Carry Small, Live Large (CSLL) is a vision held by Intel for future mobile computers. In a nutshell it is the vision of more powerful small form factor devices that are more aware of your environment and offer a more personal interaction with the user. This is a device with rich computing capabilities such as telephony, media, gaming & the Internet to name a few but this isn’t the limit. It is a platform for creating new kinds of applications and interactions as well. For example, you can imagine the new kinds of social networking applications that could be built with this device. Senior Fellow, Kevin Kahn wrote a great blog about CSLL.

On occasion when I explain CSLL to someone new to the topic, I get questions about the need to have a full-sized “usable” keyboard or better mouse input. Also common concerns are that with such a little display I won’t be able to show pictures or movies to friends or show a PowerPoint presentation to colleagues which is the perfect segue into Dynamic Composable Computing (DCC). DCC aims to enable the ability to connect to keyboards, mice, displays, and audio systems, to name just a few, dynamically and wirelessly with the mobile device. For example, you walk into a friend’s home and you want to show a group of people pictures and music from your last vacation. You “borrow” your friend’s large, wall-mounted flat-screen TV to show the pictures, the stereo system to play the music and a keyboard or remote to easily control forward and back action between pictures and videos. …and it is all done wirelessly. This is all done seamlessly and easily by dynamically discovering the devices available and enabling the mobile device to use them. Roy Want recently wrote a blog on this very subject that has more information.

To go a step further, think about the case where there are lots of devices and services available for dynamic composition. For example, if coffee shops and cafés across the globe who today are providing WiFi service also started offering tables with large LCD screens at one end for sharing pictures and videos. To share to my music they also include 7.1 Surround Sound at each booth and also provide use of full-size keyboards and mice. When I walk into such an environment, it could be a laborious task to discover the available DCC devices and then connect to the ones I want to use based on the table I’m sitting at.

My team, the Software Pathfinding and Innovation Group (SPI), within Intel’s Software and Solutions Group is focused on solving this problem along with many others with our research in a general-use Context Aware Computing (CAC) framework and engine. In our research we’ve designed and built a running prototype of a context aware computing engine. This engine provides a plug-in architecture for data collection (called Providers) from a variety of source types. The data schema is also extensible allowing 3rd parties to enhance and extend it as needed. Internal to the system it has a data collection mechanism, known as the Aggregator, making the data readily available to any number of data consumers. Also internal to the system is a programmable Analyzer which processes the context data to make higher-level conclusions from the data. Finally it contains a set of client APIs allowing applications to have access to the raw context data and analyzed data through poll-based and event-based methods. To circle back, in the coffee shop example above, this context engine can suggest to the user which booth to sit at based on the user’s preferences for display size, type of sound equipment, that fact that the user is with friends (and thus likely to share media content), the nearness to windows and so forth. It can also facilitate the composition actions once a decision is made by the user.

For IDF I along with members of my team developed a Context Aware Composition demo called “Automated Conference Room Composition” which combined features of the context engine along with the composition engine from Roy Want’s team mentioned above. Sri Sridharan, our group’s marketing guru, showed the demo which used the composition engine to discover and compose with conference room display devices (i.e. an LCD projector in this case). The context engine developed by my team was programmed to automatically compose with the projector if the following was true: LCD projector is available AND I’m the meeting owner AND I’m physically in the conference room AND I’ve sat down for the meeting. This was done through a variety of plug-in providers. A plug-in provider interacted with the composition engine to determine what projectors were available, another plug-in provider inspected my Outlook calendar to see if I had a meeting on my calendar, and another (simulated for the demo) indicated my location (at my desk vs in the conference room) and finally the last was a plug-in provider that communicated over Bluetooth with an Multiple Sensor Platform (MSP) device to determine if I was still walking, or if I had sat down to start the meeting. Once these criteria were met, the context engine automatically composed with the projector and started showing my presentation.

To summarize, the industry is in the midst of change. Mobile computers are becoming more capable and more powerful. With the CSLL efforts from Intel and the research done on Dynamic Composible Computing and Context Aware Computing you’ll have new-found capability on your mobile computer. You’ll be able to dynamically compose with devices and services to more easily interact with and more easy share your media with friends. You’ll also receive a better experience as mobile devices adapt to your ever-changing context and help you more easily make decisions and choices. You’ll be able to… Oh, wait! I’ve got to go. There’s my context aware device telling me that my next meeting got moved an hour earlier so I’d had better catch lunch soon or I’ll go hungry for the afternoon. Enjoy!

Lester Memmott is a senior software architect in the Software Pathfinding and Innovation group in Intel SSG. After employment with Novell & IBM, Lester joined Intel in 1995 and has worked in a variety of software related areas from product development to technology research. Most recently he is designing context aware technology targeted to make mobile computers easier to use. He holds two patents with others pending. He received B.S. and M.S. degrees in electrical engineering from Brigham Young University.

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Taking Multi-core Programming Into The Bazaar: An Argument for Open Source Tools

2008-04-07T17:10:10Z

All the major CPU manufacturers have thrown their lot in with multi-core designs. The (multi-billion dollar) question now is how to program these devices. I can tell you with some confidence that we don’t yet know what the answer will be in 10 years. I can’t imagine that any single company can reliably solve this problem…and I think the Open Source community is essential to finding the answer. The main reason lies in the relatively unexplored territory of how multi-core programming models interact. If I’m preaching to the choir (though not in a Cathedral…see below), feel free to skip the rest of this. However, if you’re still unconvinced, read on. Admittedly, much of this argument is not new, but I think the challenges of multi-core programming create a greater imperative.

In today’s parallel programming models, we have a variety of approaches that work now but they all have shortcomings and limitations. This isn’t so much an intrinsic problem in these languages or tools, in most cases, but a shortcoming in their implementation. Rather, it was a shortcoming in our vision; for the most part, as we invented these models, they weren’t envisioned or implemented to work together.

Getting them to work together isn’t trivial, but is do-able in most cases. (For example, we’ll often find that the underlying threading runtimes weren’t designed well to play together with others, but this can be fixed.) The real problem is that of these many choices, some will need to be mutated and many combinations will need to be tried. These models can and will be combined in thousands of interesting ways, with many different semantic implications. Each of these efforts will be risky, all being more likely to fail than succeed on the way to perfecting the model(s) and language(s) that will ultimately be used for large-scale parallel programming. Though we take risks at big companies, they are fairly risk-averse for the most part. Moreover, we tend to try to leverage our existing investments in development as much as possible. This means that a fatally flawed bet (product) is not likely to be readily tossed out as sound technical “natural selection” would require.

The experimental substrate for this evolutionary churn must be real applications, but again, we run into the risks that any (sensible) large software company must be aware of. When developing new major version of products, it is highly unlikely that the code base is completely rewritten or even significantly turned over. Estimates vary, but let’s assume that major version revisions change (often much) less than 30% of the source base. Given this, how likely is it that a major, risk-averse software developer would rewrite substantial portions (>50%) of an important application to use a combination of parallel programming models? Especially when the initial value of parallel programming (increased performance, versus longer term feature differentiation) is of limited value to the typical application? How about several such models that have never been used together?

This is the great challenge facing us and it is a daunting one. For example, in the research labs, we develop a pretty wide range of multi-core related programming technologies around data parallelism, implicit parallelism, functional programming languages, transactional memory, and speculative multithreading. We have barely begun to think about how these different models interact (we’re starting with the Pillar project).

So what is the answer? I have a strong intuition that the answer lies in the open source community, with it’s iconoclastic brilliance, unabashed bravado, fearless experimentation, enormous energy and (growing) size, and commitment to quality software development. The open source community may well be the only place where parallel programming constructs, models, libraries and compilers can be deconstructed and recombined at the scale and pace required in the coming years (see The Cathedral and the Bazaar). For recent evidence of this, look at the amazing pace of innovation in web application frameworks (Ruby on Rails is a favorite example).

Does this mean we’re abandoning differentiation in our bread-and-butter products? Hardly. There are so many other components of a platform on which companies can differentiate and compete. For chip companies, we ultimately live and die by leading with our architecture and manufacturing technologies. Programming tools are critical to delivering the value to programmers, but they are limited to the extent that access is limited.

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Gary Martz on "Cliffside" Wireless PAN technology

2008-04-01T16:26:15Z

On the eve of the Intel Developer Forum, Intel held briefings for the press today talking about the latest mobility research effort, which internally is being called Carry Small, Live Large. As part of that briefing, we showed off a new technology demonstration coming from our Mobile Products Group that I captured some video of and thought I’d post since many aren’t able to attend this event in Shanghai.

If you haven’t read Intel Senior Fellow Kevin Kahn’s blog about Carry Small, Live Large, you should check it out here. In a nutshell, Intel researchers want you to carry something as small as a Mobile Internet Device (which will only keep getting smaller) yet not lose the capabilities you currently have with your larger laptop-like device (DVD drive, USB ports for printers, CE device connection, large screen, …etc). The research projects are focused on how to accomplish this with form factors, energy efficiency, context awareness, sensors and others. “Cliffside” is a development effort specifically aimed at enabling your notebook and MID devices to communicate with and leverage other devices in the environment, so you can still “live large”.

“Cliffside” enables a single Wi-Fi adapter to function like two independent Wi-Fi adapters. This technology provides the wireless connections so you could synch your MP3 and video files without a USB cable, directly and wirelessly connect your notebook to your TV to view HD movies, have wireless connections to your personal Wi-Fi devices in your home office while having a VPN connection on your WLAN to your corporate network, or connect to other notebooks to share files and chat even when an AP isn’t available. The benefit of this technology comes from enabling Centrino users to be able to simultaneously have a connection to a WLAN (BSS) while also having a Wi-Fi Personal Area Network (BSS Wi-Fi PAN) with up to eight Wi-Fi enabled devices connected directly to their Centrino notebook. Wi-Fi PAN technology delivers direct wireless connections for synchronization and consumption of media content and files between your Centrino notebook and other Wi-Fi enabled devices such as notebooks, MIDs, MP3 players, cameras, TVs, printers, portable game players, game consoles and projectors.

Check out the video below video to see “Cliffside” working in action:

Click To Play

Gary Martz is a Marketing Producet Manager with Intel’s WiFi Personal Area Network Technology group.

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Kevin Kahn on Redefining Mobility: Carry Small, Live Large

2008-04-01T00:00:09Z

Imagine a day when a single device small enough to fit in your pocket has the power of a laptop and can deliver a rich computing, telephony, media, gaming, and Internet experience. Imagine a day when this device knows your tendencies and preferences and can adapt and optimize its interfaces to match what you are doing at any point any time. Imagine a day when this device is not constrained as a standalone unit, but can dynamically become a hybrid combination of other computing and multimedia devices in close proximity. In the labs at Intel, we have been looking at what makes sense for mobility in the future – a vision we refer to as Carry Small, Live Large.

The first component of the Carry Small, Live Large vision – Carry Small – is focused on enabling users to carry essential and convenient computing resources in powerful, small, pocket-sized devices. Today, many of us frequently carry laptops, PDAs, cellular phones, mp3 players, and other mobile devices. This mishmash of technologies is disconnected and in many cases limited in functionality. Devices are locked into specific networks and operating modes and most cannot communicate with each other. With the exception of laptops, few mobile devices deliver a true, full Internet experience. As we use different mobile devices, we have come to expect a bifurcated experience with different views of applications and Internet websites on different devices. We have conditioned ourselves to live with a suboptimal experience on small form factor devices based on what we expect the device to be capable of rather than what we really want the experience to be.

The research and development behind Carry Small technologies will produce small, powerful mobile devices, which offer multifaceted functionality. They will offer more powerful processors, allowing them to overcome shortcomings of the small form factor by supporting more natural forms of human interfaces such as voice and gesture recognition. They will be more energy efficient, and feature longer battery lives than most mobile devices today. Tomorrow’s mobile device will have ubiquitous connectivity, able to automatically recognize and connect to WiFi, WiMAX, and 3G networks, among others. Beyond improvements to the standalone device, we also believe there are also significant opportunities to improve the mobile experience through seamless connectivity and interactions with devices around you.

The second component of the Carry Small, Live Large vision – Live Large – is focused on amplifying and enhancing the utility of the small mobile device by detecting, connecting, and sharing functionality with a variety of computing, storage, and multimedia devices in their vicinity. When you walk into your office, your small mobile device should automatically and wirelessly dock with your mouse, keyboard, and display monitor, or even with the larger interfaces of a notebook PC, providing a better experience by eliminating dependency on the tiny keyboard and screen when more convenient interface devices are available. While travelling on a long flight, the mobile device should be able to utilize the screen on the back of the seat in front of you to extend battery life by powering down the small mobile screen. This vision requires technologies to discover relevant devices and allow easy, secure wireless connections to be established between them. Technologies such as near-field communication (NFC) will enable secure introductions by simply touching one device to another – an intuitive approach for end-users that is analogous to a handshake between humans.

Living Large also means that your experiences are relevant to your current context. For instance, when travelling in a foreign country, integrated sensors such as GPS, accelerometers, and a compass will allow a device to infer where you are and what you are doing. If you are looking at an interesting historic building, the device could use its built-in camera to capture what you are looking at, synthesize with contextual data such as your location and direction you are facing, and download and present historic and tourist information to you via the mobile broadband Internet connection. All of these components are available in devices as standalone functions today, but enormous opportunities are at our doorstep if we connect them together in a meaningful way.

At Intel, research is already underway to make mobile devices, smaller, smarter, and context-aware. And work is being done to ensure these devices can take advantage of other resources around them. However, we can’t fully realize this vision by working on our own. Many companies are striving to make mobile technologies smaller and more functional, and many incompatible proprietary solutions for aspects of this vision have been demonstrated at industry forums such as the Consumer Electronic Show. Standards and cooperation across both the PC and CE industries are essential to ensure a seamless experience for end-users without burdening them with the need to determine which devices are compatible and which protocol should be used for one application versus another.

It is at the intersection of Carry Small and Live Large where composable and context-aware computing capabilities become real. And it is at this intersection where our everyday experiences are greatly amplified and enriched. Help us to enable the new mobility of the future.

Dr. Kahn is an Intel Senior Fellow, the corporation’s highest technical position, and currently the Director of the Communications Technology Lab, a corporate advanced development and research lab responsible for radio, optical, and copper physical layer technologies, as well as higher level protocol work. Additionally, he helps drive communications strategies and policy for the corporation. Some of his primary current focuses are broadband access to the home, wireless LANs and PANs, spectrum policy, and related Internet issues. He currently serves on the Commerce Spectrum Advisory Committee, the FCC Technological Advisory Council, the Computer Science and Telecommunications Board of the National Research Council, and on various academic advisory committees. Throughout his 30-year career with Intel, he has worked in system software development, operating systems, processor architecture, and various strategic planning roles. He has held both management and senior individual contributor roles. He holds a B.Sc. in Mathematics from Manhattan College, and M.S. and Ph.D. in Computer Science from Purdue University.

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Yimin Zhang on Why do we need many-core?

2008-03-31T22:00:00Z

Now we are already in a Multi-core era, dual-core has become mainstream, and some people even have Quad-core CPUs in their desktop PC. But some people still are are not clear if, in the future more cores will benefit them, due to it seems that most of applications they care about have been reasonably fast in Dual-core or Quad-core. The below questions is often asked by people: Will future applications (especially desktop applications) need more cores? and what are those applications? Some people may say HPC, but other people will not be satisfied with the answer due to they are mainly concerning the applications on the PC, and normal people don’t need to run HPC applications on their desktop.

One saying is that “the best way to predict future is to invent it”, this is exactly the best strategy we answer these questions about future. Instead of just lieing on the bed dreaming about future applications, Intel researchers are actively working with academia to invent future applications for future multi-core and many-core in the last few years. These applicatoins are named RMS (recognition, mining, synthesis), and now it has a new name “Model based computing”.

As I see it, the commonality of these applications is large amount of data processing in short time or even realtime, some examples are synthesis of virtual world, or analyzing large amount of video data based on computer vision technques. Here at Intel China Research Center, we are actively conducting research on this. One of the important application field we are working on is media search/mining, that is doing content analysis of the media data and make it easy for people to use it. Through our research collaboration with academia in the last 3 years, we have developed some leading edge technology that can enable a wide area of applications even now，e.g. search, browsing, editing, summarization etc. We are working with our partners to deploy these technology to the market. It will be great that more and more people can join this effort to develop more applications for multi-core. We believe in the near future we will see less and less people bother to ask “why I need multi-core”, instead more and more people will ask “when can I get more cores to run my applications faster”. I believe that day is not far away. And we will be proud that we contributed to this.

I will co-teach a session “The Demand for Many Cores: Tera-scale Usage Models” at the coming IDF at Shanghai with my US colleague Dr. Jerry Bautista，which will give more details. Welcome to come join this session then. I’m glad to discuss with you more then.

Yimin Zhang is a research manager in the Architecture Research Lab in the Intel China Research Center lab in Beijing.

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Wireless Displays: To Compress or Not Compress

2008-03-28T15:00:00Z

This years CES was filled with a variety of wireless display and wireless HDMI solutions using various combinations of radios (proprietary radios in the UWB or 5 GHz unlicensed bands, WiFi-based, UWB/W-USB based, and 60 GHz based) and compression algorithms (uncompressed, proprietary lossless and lossy, JPEG2000 based, and H.264 based). So, it appears there is interest in the industry to enable this usage model, but how can we reign in all this chaos? Clearly, lots of industry harmonization and standards will be needed before this application can really be ubiquitous. There will be a session on wireless displays during the Intel Developer Forum (IDF) in April which we hope will spark further discussion and collaboration in this area.

Rather than trying to address all the issues related to the wireless display area, I’d like to focus this discussion on compression for short-range wireless applications. Depending on who you talk to and what their background is, there appears to be a number of different opinions on whether compression can meet the quality demands for this application (in short, trying to replace the HDMI or video cable via a wireless link). Clearly, replacing a wire with the same quality over wireless is not a trivial task, and the goal would be to have ‘visually lossless quality’ (i.e., the end user cannot see the difference between the wire and wireless). So, can compression (any kind of compression) meet this strict requirement?

Let’s first ask the question, ‘Why not send video and display content uncompressed’? As an example, a 1080p resolution screen requires approximately a 3 Gbps link. Existing radios (UWB and WiFi based) clearly can’t meet these rates today and so some form of compression would be needed, but future 60 GHz radios might. So, assuming I had a 3+ Gbps radio, is it still best to send video streams uncompressed? What if I had other devices that wanted to share that bandwidth (for large file transfers, for example)? What if I wanted to support more than one screen? What happens as the screen resolutions increase over time, and what happens to my wireless bandwidth needs (will radio throughput be able to keep up with display resolutions)? And finally, aren’t you burning a lot of power continuously transmitting at a constant 3 Gbps rate or higher? Hopefully, these questions suggest that the answer of sending video content uncompressed is not obvious even if the radio is capable of doing so, and there are a number of engineering trade-offs that have to be explored.

So, what if we were able to achieve comparable quality (where a consumer can’t tell the difference between compressed and uncompressed) with just a fraction of the throughput (say, 1/10 or 1/20 or even less)? Why wouldn’t we want to do that? I agree that this will require some complex circuits to achieve, but process scaling should keep this impact relatively small. If this were possible, what can I do with it? I can reduce my radio usage by, say, 1/10, and save roughly 90% of my radio power (you won’t be able to turn off all radio circuits, but this is just for explanation). I can increase my range by a factor of 3, or I can better go through a cabinet or wall. For some applications, like PC displays, very little is changing on the screen at any one time, and so I can achieve an overall reduction in average throughput (and power consumption) by a factor of 100 or even a 1,000. For the last example, this could be done while even maintaining mathematically lossless quality by implementing simple temporal compression and a lossless codec. So, aren’t these benefits worth exploring, even if we had a multi-Gbps radio? Of course, my opinion is yes. Also, it seems that some of these advantages could also benefit wired displays…at least is should be worth exploring for future generation HDMI and DisplayPort interfaces.

The first hurdle to overcome with compression is quality, and whether or not it can meet consumer demands. Recognize that virtually all video content is compressed at one stage or another before a person sees it. So, we’re already viewing compressed content, which should give hope that it’s possible. Clearly, there are cases where we don’t have access to compressed content (like a PC display, or video game), and so we would need to be able to compress in real-time. In order to be convinced, people really have to see it to believe it. I have spoken to several skeptics and have found that people are genuinely surprised at the quality that can be achieved even with a fairly low compression ratio (1/20 and smaller) using some of the current state-of-the-art codecs like H.264. So, I would encourage people to explore for themselves first (for example, see some of the demos at IDF in April in China and others shown at CES), and then consider the benefits that could be possible if compression can satisfy consumer demands in quality. Of course, we also have to keep overall latency, cost, and power low as well, which should be part of the evolution of the technology.

I recognize that compression is just one piece of the puzzle to enable wireless displays. Clearly, the performance has to be proven over a wireless channel (error recovery mechanisms needed), content protection must be addressed to protect the premium content, audio/video synchronization must be wire equivalent, etc. These are the kinds of problem engineers love to attack, and I have no doubt novel solutions for these can be achieved. So, I think we should take a fresh look at compression technology for short-range video and display transport (for both wireless and wired), and see what new benefits and usage models can be enabled by it.

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Vic Lortz on Amplifying your Mobile Experience

2008-03-27T23:33:31Z

Intel is in the enabling game. As a building block supplier, our business is based on the premise that when our customers win, we win, too. We are also in an industry that is constantly pursuing the next big thing to drive new waves of growth and business opportunities. The Mobile Internet Device (MID) category is a candidate for the “next big thing” in mobile computing, although some skeptics question its appeal.

By its very name, it is obvious that a MID will connect to the Internet and consume Internet content and services. However, the “Mobile” part of the name suggests that the resulting experience may have the user interface limitations typical of small devices. A MID may have a bigger screen than a typical mobile phone, but it can’t be dramatically bigger without becoming the equivalent of a notebook or tablet PC.

So, will the MID end up being too small (or too large) to be the next big thing? Maybe, maybe not. I think part of the answer lies in thinking outside of the MID box and recognizing the potential of connecting MIDs to other devices around it. For example, digital TVs have big screens capable of delivering a compelling visual experience. Imagine if digital TVs included a wireless display feature (either integrated or through an external adapter) so that a MID could easily use that large display instead of or in addition to the integrated screen of the MID. It is not much of a stretch to see the possibilities around this combination of technologies.

However, as Edison said, genius is 1% inspiration and 99% perspiration. It is going to take a lot of collective industry perspiration to enable broad deployment of technologies such as wireless remote displays and compatible mobile devices in such a way that the non-geniuses of the world will be able to make it all work.

Intel is working on this and other similar problems together with fellow-travelers in the industry. As we identify the necessary set of technologies and standards to support, we will integrate them into our next-generation mobile devices (both laptops and MIDs). If we succeed, the MID may confound its detractors and become the next big thing after all. Then the OEMs who use Intel’s mobile platforms will have great opportunities to pursue that next wave of growth, and we will grow along with them. After all, Intel is in the enabling game.

Vic Lortz is a Research Scientist and senior architect at Intel’s Communications Technology Lab in Hillsboro, Oregon. He holds a B.A. degree in Physics and a M.S. and Ph.D. in Computer science. In his Ph.D. research at the University of Michigan, he developed methods for time-bounded resource sharing on multiprocessors for hard real-time applications such as machine control and robotics. Since joining Intel in 1994, Vic has focused primarily on technologies related to home networking and wireless network security. He has participated in numerous standards activities, including serving as chair of UPnP Security in 2003 and lead architect and co-editor of Wi-Fi Protected Setup in 2006.

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